413 lines
12 KiB
C
413 lines
12 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/timer.c
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* @author Marti Bolivar <mbolivar@leaflabs.com>
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* @brief Portable timer routines.
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*/
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#include <libmaple/timer.h>
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#include <libmaple/stm32.h>
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#include "timer_private.h"
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static void disable_channel(timer_dev *dev, uint8 channel);
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static void pwm_mode(timer_dev *dev, uint8 channel);
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static void output_compare_mode(timer_dev *dev, uint8 channel);
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static inline void enable_irq(timer_dev *dev, timer_interrupt_id iid);
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/*
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* Devices
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*
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* Defer to the timer_private API for declaring these.
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*/
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#if STM32_HAVE_TIMER(1)
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static timer_dev timer1 = ADVANCED_TIMER(1);
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/** Timer 1 device (advanced) */
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timer_dev *TIMER1 = &timer1;
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#endif
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#if STM32_HAVE_TIMER(2)
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static timer_dev timer2 = GENERAL_TIMER(2);
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/** Timer 2 device (general-purpose) */
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timer_dev *TIMER2 = &timer2;
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#endif
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#if STM32_HAVE_TIMER(3)
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static timer_dev timer3 = GENERAL_TIMER(3);
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/** Timer 3 device (general-purpose) */
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timer_dev *TIMER3 = &timer3;
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#endif
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#if STM32_HAVE_TIMER(4)
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static timer_dev timer4 = GENERAL_TIMER(4);
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/** Timer 4 device (general-purpose) */
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timer_dev *TIMER4 = &timer4;
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#endif
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#if STM32_HAVE_TIMER(5)
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static timer_dev timer5 = GENERAL_TIMER(5);
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/** Timer 5 device (general-purpose) */
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timer_dev *TIMER5 = &timer5;
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#endif
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#if STM32_HAVE_TIMER(6)
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static timer_dev timer6 = BASIC_TIMER(6);
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/** Timer 6 device (basic) */
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timer_dev *TIMER6 = &timer6;
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#endif
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#if STM32_HAVE_TIMER(7)
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static timer_dev timer7 = BASIC_TIMER(7);
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/** Timer 7 device (basic) */
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timer_dev *TIMER7 = &timer7;
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#endif
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#if STM32_HAVE_TIMER(8)
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static timer_dev timer8 = ADVANCED_TIMER(8);
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/** Timer 8 device (advanced) */
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timer_dev *TIMER8 = &timer8;
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#endif
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#if STM32_HAVE_TIMER(9)
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static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT);
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/** Timer 9 device (general-purpose) */
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timer_dev *TIMER9 = &timer9;
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#endif
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#if STM32_HAVE_TIMER(10)
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static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT);
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/** Timer 10 device (general-purpose) */
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timer_dev *TIMER10 = &timer10;
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#endif
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#if STM32_HAVE_TIMER(11)
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static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT);
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/** Timer 11 device (general-purpose) */
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timer_dev *TIMER11 = &timer11;
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#endif
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#if STM32_HAVE_TIMER(12)
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static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT);
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/** Timer 12 device (general-purpose) */
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timer_dev *TIMER12 = &timer12;
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#endif
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#if STM32_HAVE_TIMER(13)
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static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT);
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/** Timer 13 device (general-purpose) */
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timer_dev *TIMER13 = &timer13;
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#endif
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#if STM32_HAVE_TIMER(14)
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static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT);
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/** Timer 14 device (general-purpose) */
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timer_dev *TIMER14 = &timer14;
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#endif
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/*
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* Routines
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*/
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/**
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* @brief Call a function on timer devices.
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* @param fn Function to call on each timer device.
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*/
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void timer_foreach(void (*fn)(timer_dev*)) {
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#if STM32_HAVE_TIMER(1)
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fn(TIMER1);
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#endif
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#if STM32_HAVE_TIMER(2)
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fn(TIMER2);
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#endif
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#if STM32_HAVE_TIMER(3)
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fn(TIMER3);
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#endif
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#if STM32_HAVE_TIMER(4)
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fn(TIMER4);
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#endif
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#if STM32_HAVE_TIMER(5)
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fn(TIMER5);
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#endif
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#if STM32_HAVE_TIMER(6)
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fn(TIMER6);
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#endif
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#if STM32_HAVE_TIMER(7)
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fn(TIMER7);
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#endif
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#if STM32_HAVE_TIMER(8)
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fn(TIMER8);
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#endif
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#if STM32_HAVE_TIMER(9)
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fn(TIMER9);
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#endif
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#if STM32_HAVE_TIMER(10)
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fn(TIMER10);
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#endif
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#if STM32_HAVE_TIMER(11)
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fn(TIMER11);
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#endif
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#if STM32_HAVE_TIMER(12)
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fn(TIMER12);
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#endif
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#if STM32_HAVE_TIMER(13)
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fn(TIMER13);
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#endif
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#if STM32_HAVE_TIMER(14)
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fn(TIMER14);
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#endif
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}
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/**
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* Initialize a timer, and reset its register map.
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* @param dev Timer to initialize
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*/
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void timer_init(timer_dev *dev) {
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rcc_clk_enable(dev->clk_id);
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rcc_reset_dev(dev->clk_id);
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}
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/**
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* @brief Disable a timer.
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*
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* The timer will stop counting, all DMA requests and interrupts will
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* be disabled, and no state changes will be output.
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*
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* @param dev Timer to disable.
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*/
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void timer_disable(timer_dev *dev) {
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(dev->regs).bas->CR1 = 0;
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(dev->regs).bas->DIER = 0;
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switch (dev->type) {
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case TIMER_ADVANCED: /* fall-through */
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case TIMER_GENERAL:
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(dev->regs).gen->CCER = 0;
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break;
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case TIMER_BASIC:
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break;
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}
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}
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/**
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* Sets the mode of an individual timer channel.
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*
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* Note that not all timers can be configured in every mode. For
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* example, basic timers cannot be configured to output compare mode.
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* Be sure to use a timer which is appropriate for the mode you want.
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*
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* @param dev Timer whose channel mode to set
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* @param channel Relevant channel
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* @param mode New timer mode for channel
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*/
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void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) {
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ASSERT_FAULT(channel > 0 && channel <= 4);
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/* TODO decide about the basic timers */
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ASSERT(dev->type != TIMER_BASIC);
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if (dev->type == TIMER_BASIC)
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return;
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switch (mode) {
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case TIMER_DISABLED:
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disable_channel(dev, channel);
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break;
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case TIMER_PWM:
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pwm_mode(dev, channel);
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break;
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case TIMER_OUTPUT_COMPARE:
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output_compare_mode(dev, channel);
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break;
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}
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}
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/**
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* @brief Determine whether a timer has a particular capture/compare channel.
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*
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* Different timers have different numbers of capture/compare channels
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* (and some have none at all). Use this function to test whether a
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* given timer/channel combination will work.
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*
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* @param dev Timer device
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* @param channel Capture/compare channel, from 1 to 4
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* @return Nonzero if dev has channel, zero otherwise.
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*/
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int timer_has_cc_channel(timer_dev *dev, uint8 channel) {
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/* On all currently supported series: advanced and "full-featured"
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* general purpose timers have all four channels. Of the
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* restricted general timers, timers 9 and 12 have channels 1 and
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* 2; the others have channel 1 only. Basic timers have none. */
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rcc_clk_id id = dev->clk_id;
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ASSERT((1 <= channel) && (channel <= 4));
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if (id <= RCC_TIMER5 || id == RCC_TIMER8) {
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return 1; /* 1 and 8 are advanced, 2-5 are "full" general */
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} else if (id <= RCC_TIMER7) {
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return 0; /* 6 and 7 are basic */
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}
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/* The rest are restricted general. */
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return (((id == RCC_TIMER9 || id == RCC_TIMER12) && channel <= 2) ||
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channel == 1);
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}
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/**
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* @brief Attach a timer interrupt.
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* @param dev Timer device
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* @param interrupt Interrupt number to attach to; this may be any
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* timer_interrupt_id or timer_channel value appropriate
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* for the timer.
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* @param handler Handler to attach to the given interrupt.
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* @see timer_interrupt_id
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* @see timer_channel
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*/
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void timer_attach_interrupt(timer_dev *dev,
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uint8 interrupt,
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voidFuncPtr handler) {
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dev->handlers[interrupt] = handler;
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timer_enable_irq(dev, interrupt);
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enable_irq(dev, interrupt);
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}
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/**
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* @brief Detach a timer interrupt.
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* @param dev Timer device
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* @param interrupt Interrupt number to detach; this may be any
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* timer_interrupt_id or timer_channel value appropriate
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* for the timer.
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* @see timer_interrupt_id
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* @see timer_channel
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*/
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void timer_detach_interrupt(timer_dev *dev, uint8 interrupt) {
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timer_disable_irq(dev, interrupt);
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dev->handlers[interrupt] = NULL;
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}
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/*
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* Utilities
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*/
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static void disable_channel(timer_dev *dev, uint8 channel) {
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timer_detach_interrupt(dev, channel);
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timer_cc_disable(dev, channel);
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}
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static void pwm_mode(timer_dev *dev, uint8 channel) {
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timer_disable_irq(dev, channel);
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timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE);
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timer_cc_enable(dev, channel);
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}
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static void output_compare_mode(timer_dev *dev, uint8 channel) {
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timer_oc_set_mode(dev, channel, TIMER_OC_MODE_ACTIVE_ON_MATCH, 0);
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timer_cc_enable(dev, channel);
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}
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static void enable_adv_irq(timer_dev *dev, timer_interrupt_id id);
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static void enable_bas_gen_irq(timer_dev *dev);
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static inline void enable_irq(timer_dev *dev, timer_interrupt_id iid) {
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if (dev->type == TIMER_ADVANCED) {
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enable_adv_irq(dev, iid);
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} else {
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enable_bas_gen_irq(dev);
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}
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}
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/* Advanced control timers have several IRQ lines corresponding to
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* different timer interrupts.
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*
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* Note: This function assumes that the only advanced timers are TIM1
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* and TIM8, and needs the obvious changes if that assumption is
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* violated by a later STM32 series. */
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static void enable_adv_irq(timer_dev *dev, timer_interrupt_id id) {
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uint8 is_tim1 = dev->clk_id == RCC_TIMER1;
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nvic_irq_num irq_num;
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switch (id) {
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case TIMER_UPDATE_INTERRUPT:
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irq_num = (is_tim1 ?
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NVIC_TIMER1_UP_TIMER10 :
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NVIC_TIMER8_UP_TIMER13);
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break;
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case TIMER_CC1_INTERRUPT: /* Fall through */
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case TIMER_CC2_INTERRUPT: /* ... */
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case TIMER_CC3_INTERRUPT: /* ... */
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case TIMER_CC4_INTERRUPT:
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irq_num = is_tim1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC;
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break;
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case TIMER_COM_INTERRUPT: /* Fall through */
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case TIMER_TRG_INTERRUPT:
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irq_num = (is_tim1 ?
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NVIC_TIMER1_TRG_COM_TIMER11 :
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NVIC_TIMER8_TRG_COM_TIMER14);
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break;
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case TIMER_BREAK_INTERRUPT:
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irq_num = (is_tim1 ?
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NVIC_TIMER1_BRK_TIMER9 :
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NVIC_TIMER8_BRK_TIMER12);
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break;
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default:
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/* Can't happen, but placate the compiler */
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ASSERT(0);
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return;
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}
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nvic_irq_enable(irq_num);
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}
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/* Basic and general purpose timers have a single IRQ line, which is
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* shared by all interrupts supported by a particular timer. */
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static void enable_bas_gen_irq(timer_dev *dev) {
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nvic_irq_num irq_num;
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switch (dev->clk_id) {
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case RCC_TIMER2:
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irq_num = NVIC_TIMER2;
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break;
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case RCC_TIMER3:
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irq_num = NVIC_TIMER3;
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break;
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case RCC_TIMER4:
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irq_num = NVIC_TIMER4;
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break;
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case RCC_TIMER5:
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irq_num = NVIC_TIMER5;
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break;
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case RCC_TIMER6:
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irq_num = NVIC_TIMER6;
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break;
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case RCC_TIMER7:
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irq_num = NVIC_TIMER7;
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break;
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case RCC_TIMER9:
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irq_num = NVIC_TIMER1_BRK_TIMER9;
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break;
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case RCC_TIMER10:
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irq_num = NVIC_TIMER1_UP_TIMER10;
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break;
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case RCC_TIMER11:
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irq_num = NVIC_TIMER1_TRG_COM_TIMER11;
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break;
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case RCC_TIMER12:
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irq_num = NVIC_TIMER8_BRK_TIMER12;
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break;
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case RCC_TIMER13:
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irq_num = NVIC_TIMER8_UP_TIMER13;
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break;
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case RCC_TIMER14:
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irq_num = NVIC_TIMER8_TRG_COM_TIMER14;
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break;
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default:
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ASSERT_FAULT(0);
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return;
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}
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nvic_irq_enable(irq_num);
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}
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