6d1ebe4a67
Various changes to Doxygen structure, to help leaflabs-docs make sense of everything. Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
176 lines
6.4 KiB
C
176 lines
6.4 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f2/rcc.c
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* @brief STM32F2 RCC.
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*/
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#include <libmaple/rcc.h>
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#include <libmaple/libmaple.h>
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#include "rcc_private.h"
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#define DEV_ENTRY(domain, dev) \
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{.clk_domain = RCC_##domain, .line_num = RCC_##domain##ENR_##dev##EN_BIT}
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const struct rcc_dev_info rcc_dev_table[] = {
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/* AHB1 */
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[RCC_OTGHSULPI] = DEV_ENTRY(AHB1, OTGHSULPI),
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[RCC_OTGHS] = DEV_ENTRY(AHB1, OTGHS),
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[RCC_ETHMACPTP] = DEV_ENTRY(AHB1, ETHMACPTP),
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[RCC_ETHMACRX] = DEV_ENTRY(AHB1, ETHMACRX),
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[RCC_ETHMACTX] = DEV_ENTRY(AHB1, ETHMACTX),
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[RCC_ETHMAC] = DEV_ENTRY(AHB1, ETHMAC),
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[RCC_DMA2] = DEV_ENTRY(AHB1, DMA2),
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[RCC_DMA1] = DEV_ENTRY(AHB1, DMA1),
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[RCC_BKPSRAM] = DEV_ENTRY(AHB1, BKPSRAM),
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[RCC_CRC] = DEV_ENTRY(AHB1, CRC),
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[RCC_GPIOI] = DEV_ENTRY(AHB1, GPIOI),
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[RCC_GPIOH] = DEV_ENTRY(AHB1, GPIOH),
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[RCC_GPIOG] = DEV_ENTRY(AHB1, GPIOG),
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[RCC_GPIOF] = DEV_ENTRY(AHB1, GPIOF),
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[RCC_GPIOE] = DEV_ENTRY(AHB1, GPIOE),
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[RCC_GPIOD] = DEV_ENTRY(AHB1, GPIOD),
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[RCC_GPIOC] = DEV_ENTRY(AHB1, GPIOC),
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[RCC_GPIOB] = DEV_ENTRY(AHB1, GPIOB),
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[RCC_GPIOA] = DEV_ENTRY(AHB1, GPIOA),
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/* AHB2 */
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[RCC_OTGFS] = DEV_ENTRY(AHB2, OTGFS),
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[RCC_RNG] = DEV_ENTRY(AHB2, RNG),
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[RCC_HASH] = DEV_ENTRY(AHB2, HASH),
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[RCC_CRYP] = DEV_ENTRY(AHB2, CRYP),
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[RCC_DCMI] = DEV_ENTRY(AHB2, DCMI),
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/* AHB3 */
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[RCC_FSMC] = DEV_ENTRY(AHB3, FSMC),
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/* APB1 */
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[RCC_DAC] = DEV_ENTRY(APB1, DAC),
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[RCC_PWR] = DEV_ENTRY(APB1, PWR),
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[RCC_CAN2] = DEV_ENTRY(APB1, CAN2),
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[RCC_CAN1] = DEV_ENTRY(APB1, CAN1),
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[RCC_I2C3] = DEV_ENTRY(APB1, I2C3),
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[RCC_I2C2] = DEV_ENTRY(APB1, I2C2),
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[RCC_I2C1] = DEV_ENTRY(APB1, I2C1),
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[RCC_UART5] = DEV_ENTRY(APB1, UART5),
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[RCC_UART4] = DEV_ENTRY(APB1, UART4),
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[RCC_USART3] = DEV_ENTRY(APB1, USART3),
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[RCC_USART2] = DEV_ENTRY(APB1, USART2),
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[RCC_SPI3] = DEV_ENTRY(APB1, SPI3),
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[RCC_SPI2] = DEV_ENTRY(APB1, SPI2),
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[RCC_WWDG] = DEV_ENTRY(APB1, WWDG),
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[RCC_TIMER14] = DEV_ENTRY(APB1, TIM14),
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[RCC_TIMER13] = DEV_ENTRY(APB1, TIM13),
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[RCC_TIMER12] = DEV_ENTRY(APB1, TIM12),
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[RCC_TIMER7] = DEV_ENTRY(APB1, TIM7),
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[RCC_TIMER6] = DEV_ENTRY(APB1, TIM6),
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[RCC_TIMER5] = DEV_ENTRY(APB1, TIM5),
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[RCC_TIMER4] = DEV_ENTRY(APB1, TIM4),
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[RCC_TIMER3] = DEV_ENTRY(APB1, TIM3),
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[RCC_TIMER2] = DEV_ENTRY(APB1, TIM2),
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/* APB2 */
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[RCC_TIMER11] = DEV_ENTRY(APB2, TIM11),
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[RCC_TIMER10] = DEV_ENTRY(APB2, TIM10),
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[RCC_TIMER9] = DEV_ENTRY(APB2, TIM9),
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[RCC_SYSCFG] = DEV_ENTRY(APB2, SYSCFG),
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[RCC_SPI1] = DEV_ENTRY(APB2, SPI1),
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[RCC_SDIO] = DEV_ENTRY(APB2, SDIO),
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[RCC_ADC3] = DEV_ENTRY(APB2, ADC3),
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[RCC_ADC2] = DEV_ENTRY(APB2, ADC2),
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[RCC_ADC1] = DEV_ENTRY(APB2, ADC1),
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[RCC_USART6] = DEV_ENTRY(APB2, USART6),
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[RCC_USART1] = DEV_ENTRY(APB2, USART1),
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[RCC_TIMER8] = DEV_ENTRY(APB2, TIM8),
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[RCC_TIMER1] = DEV_ENTRY(APB2, TIM1),
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};
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void rcc_clk_enable(rcc_clk_id id) {
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static __io uint32* enable_regs[] = {
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[RCC_AHB1] = &RCC_BASE->AHB1ENR,
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[RCC_AHB2] = &RCC_BASE->AHB2ENR,
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[RCC_AHB3] = &RCC_BASE->AHB3ENR,
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[RCC_APB1] = &RCC_BASE->APB1ENR,
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[RCC_APB2] = &RCC_BASE->APB2ENR,
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};
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rcc_do_clk_enable(enable_regs, id);
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}
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void rcc_reset_dev(rcc_clk_id id) {
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static __io uint32* reset_regs[] = {
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[RCC_AHB1] = &RCC_BASE->AHB1RSTR,
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[RCC_AHB2] = &RCC_BASE->AHB2RSTR,
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[RCC_AHB3] = &RCC_BASE->AHB3RSTR,
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[RCC_APB1] = &RCC_BASE->AHB3RSTR,
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[RCC_APB2] = &RCC_BASE->AHB3RSTR,
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};
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rcc_do_reset_dev(reset_regs, id);
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}
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void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
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static const uint32 masks[] = {
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[RCC_PRESCALER_MCO2] = RCC_CFGR_MCO2PRE,
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[RCC_PRESCALER_MCO1] = RCC_CFGR_MCO1PRE,
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[RCC_PRESCALER_RTC] = RCC_CFGR_RTCPRE,
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[RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
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[RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
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[RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
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};
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rcc_do_set_prescaler(masks, prescaler, divider);
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}
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/* pll_cfg->data must point to a struct stm32f2_rcc_pll_data. */
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void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
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stm32f2_rcc_pll_data *data = pll_cfg->data;
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uint32 pllcfgr;
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/* Check that the PLL is disabled. */
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ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
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/* Sanity-check all the parameters */
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ASSERT_FAULT((data->pllq >= 4) && (data->pllq <= 15));
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ASSERT_FAULT((data->pllp >= 2) && (data->pllp <= 8));
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ASSERT_FAULT(!(data->pllp & 1));
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ASSERT_FAULT((data->plln >= 192) && (data->plln <= 432));
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ASSERT_FAULT((data->pllm >= 2) && (data->pllm <= 63));
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/* Update RCC_PLLCFGR to reflect new values. */
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pllcfgr = RCC_BASE->PLLCFGR;
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pllcfgr &= ~(RCC_PLLCFGR_PLLQ |
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RCC_PLLCFGR_PLLP |
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RCC_PLLCFGR_PLLN |
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RCC_PLLCFGR_PLLM |
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RCC_PLLCFGR_PLLSRC);
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pllcfgr |= (pll_cfg->pllsrc |
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(data->pllq << 24) |
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(((data->pllp >> 1) - 1) << 16) |
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(data->plln << 6) |
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data->pllm);
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RCC_BASE->PLLCFGR = pllcfgr;
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}
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