323 lines
12 KiB
ArmAsm
323 lines
12 KiB
ArmAsm
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/* STM32F2 ISR weak declarations */
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.thumb
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/* Default handler, as with STM32F1 */
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.globl __default_handler
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.type __default_handler, %function
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__default_handler:
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b .
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.weak __exc_nmi
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.globl __exc_nmi
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.set __exc_nmi, __default_handler
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.weak __exc_hardfault
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.globl __exc_hardfault
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.set __exc_hardfault, __default_handler
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.weak __exc_memmanage
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.globl __exc_memmanage
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.set __exc_memmanage, __default_handler
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.weak __exc_busfault
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.globl __exc_busfault
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.set __exc_busfault, __default_handler
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.weak __exc_usagefault
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.globl __exc_usagefault
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.set __exc_usagefault, __default_handler
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.weak __stm32reservedexception7
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.globl __stm32reservedexception7
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.set __stm32reservedexception7, __default_handler
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.weak __stm32reservedexception8
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.globl __stm32reservedexception8
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.set __stm32reservedexception8, __default_handler
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.weak __stm32reservedexception9
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.globl __stm32reservedexception9
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.set __stm32reservedexception9, __default_handler
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.weak __stm32reservedexception10
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.globl __stm32reservedexception10
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.set __stm32reservedexception10, __default_handler
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.weak __exc_svc
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.globl __exc_svc
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.set __exc_svc, __default_handler
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.weak __exc_debug_monitor
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.globl __exc_debug_monitor
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.set __exc_debug_monitor, __default_handler
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.weak __stm32reservedexception13
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.globl __stm32reservedexception13
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.set __stm32reservedexception13, __default_handler
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.weak __exc_pendsv
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.globl __exc_pendsv
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.set __exc_pendsv, __default_handler
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.weak __exc_systick
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.globl __exc_systick
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.set __exc_systick, __default_handler
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.weak __irq_wwdg
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.globl __irq_wwdg
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.set __irq_wwdg, __default_handler
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.weak __irq_pvd
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.globl __irq_pvd
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.set __irq_pvd, __default_handler
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.weak __irq_tamp_stamp
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.globl __irq_tamp_stamp
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.set __irq_tamp_stamp, __default_handler
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.weak __irq_rtc_wkup
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.globl __irq_rtc_wkup
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.set __irq_rtc_wkup, __default_handler
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.weak __irq_flash
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.globl __irq_flash
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.set __irq_flash, __default_handler
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.weak __irq_rcc
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.globl __irq_rcc
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.set __irq_rcc, __default_handler
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.weak __irq_exti0
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.globl __irq_exti0
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.set __irq_exti0, __default_handler
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.weak __irq_exti1
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.globl __irq_exti1
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.set __irq_exti1, __default_handler
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.weak __irq_exti2
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.globl __irq_exti2
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.set __irq_exti2, __default_handler
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.weak __irq_exti3
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.globl __irq_exti3
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.set __irq_exti3, __default_handler
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.weak __irq_exti4
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.globl __irq_exti4
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.set __irq_exti4, __default_handler
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.weak __irq_dma1_stream0
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.globl __irq_dma1_stream0
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.set __irq_dma1_stream0, __default_handler
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.weak __irq_dma1_stream1
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.globl __irq_dma1_stream1
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.set __irq_dma1_stream1, __default_handler
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.weak __irq_dma1_stream2
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.globl __irq_dma1_stream2
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.set __irq_dma1_stream2, __default_handler
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.weak __irq_dma1_stream3
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.globl __irq_dma1_stream3
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.set __irq_dma1_stream3, __default_handler
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.weak __irq_dma1_stream4
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.globl __irq_dma1_stream4
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.set __irq_dma1_stream4, __default_handler
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.weak __irq_dma1_stream5
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.globl __irq_dma1_stream5
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.set __irq_dma1_stream5, __default_handler
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.weak __irq_dma1_stream6
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.globl __irq_dma1_stream6
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.set __irq_dma1_stream6, __default_handler
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.weak __irq_adc
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.globl __irq_adc
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.set __irq_adc, __default_handler
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.weak __irq_can1_tx
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.globl __irq_can1_tx
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.set __irq_can1_tx, __default_handler
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.weak __irq_can1_rx0
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.globl __irq_can1_rx0
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.set __irq_can1_rx0, __default_handler
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.weak __irq_can1_rx1
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.globl __irq_can1_rx1
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.set __irq_can1_rx1, __default_handler
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.weak __irq_can1_sce
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.globl __irq_can1_sce
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.set __irq_can1_sce, __default_handler
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.weak __irq_exti9_5
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.globl __irq_exti9_5
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.set __irq_exti9_5, __default_handler
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.weak __irq_tim1_brk_tim9
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.globl __irq_tim1_brk_tim9
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.set __irq_tim1_brk_tim9, __default_handler
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.weak __irq_tim1_up_tim10
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.globl __irq_tim1_up_tim10
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.set __irq_tim1_up_tim10, __default_handler
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.weak __irq_tim1_trg_com_tim11
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.globl __irq_tim1_trg_com_tim11
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.set __irq_tim1_trg_com_tim11, __default_handler
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.weak __irq_tim1_cc
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.globl __irq_tim1_cc
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.set __irq_tim1_cc, __default_handler
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.weak __irq_tim2
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.globl __irq_tim2
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.set __irq_tim2, __default_handler
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.weak __irq_tim3
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.globl __irq_tim3
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.set __irq_tim3, __default_handler
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.weak __irq_tim4
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.globl __irq_tim4
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.set __irq_tim4, __default_handler
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.weak __irq_i2c1_ev
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.globl __irq_i2c1_ev
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.set __irq_i2c1_ev, __default_handler
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.weak __irq_i2c1_er
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.globl __irq_i2c1_er
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.set __irq_i2c1_er, __default_handler
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.weak __irq_i2c2_ev
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.globl __irq_i2c2_ev
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.set __irq_i2c2_ev, __default_handler
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.weak __irq_i2c2_er
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.globl __irq_i2c2_er
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.set __irq_i2c2_er, __default_handler
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.weak __irq_spi1
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.globl __irq_spi1
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.set __irq_spi1, __default_handler
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.weak __irq_spi2
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.globl __irq_spi2
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.set __irq_spi2, __default_handler
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.weak __irq_usart1
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.globl __irq_usart1
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.set __irq_usart1, __default_handler
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.weak __irq_usart2
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.globl __irq_usart2
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.set __irq_usart2, __default_handler
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.weak __irq_usart3
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.globl __irq_usart3
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.set __irq_usart3, __default_handler
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.weak __irq_exti15_10
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.globl __irq_exti15_10
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.set __irq_exti15_10, __default_handler
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.weak __irq_rtc_alarm
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.globl __irq_rtc_alarm
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.set __irq_rtc_alarm, __default_handler
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.weak __irq_otg_fs_wkup
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.globl __irq_otg_fs_wkup
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.set __irq_otg_fs_wkup, __default_handler
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.weak __irq_tim8_brk_tim12
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.globl __irq_tim8_brk_tim12
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.set __irq_tim8_brk_tim12, __default_handler
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.weak __irq_tim8_up_tim13
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.globl __irq_tim8_up_tim13
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.set __irq_tim8_up_tim13, __default_handler
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.weak __irq_tim8_trg_com_tim14
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.globl __irq_tim8_trg_com_tim14
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.set __irq_tim8_trg_com_tim14, __default_handler
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.weak __irq_tim8_cc
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.globl __irq_tim8_cc
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.set __irq_tim8_cc, __default_handler
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.weak __irq_dma1_stream7
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.globl __irq_dma1_stream7
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.set __irq_dma1_stream7, __default_handler
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.weak __irq_fsmc
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.globl __irq_fsmc
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.set __irq_fsmc, __default_handler
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.weak __irq_sdio
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.globl __irq_sdio
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.set __irq_sdio, __default_handler
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.weak __irq_tim5
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.globl __irq_tim5
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.set __irq_tim5, __default_handler
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.weak __irq_spi3
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.globl __irq_spi3
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.set __irq_spi3, __default_handler
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.weak __irq_uart4
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.globl __irq_uart4
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.set __irq_uart4, __default_handler
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.weak __irq_uart5
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.globl __irq_uart5
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.set __irq_uart5, __default_handler
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.weak __irq_tim6_dac
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.globl __irq_tim6_dac
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.set __irq_tim6_dac, __default_handler
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.weak __irq_tim7
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.globl __irq_tim7
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.set __irq_tim7, __default_handler
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.weak __irq_dma2_stream0
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.globl __irq_dma2_stream0
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.set __irq_dma2_stream0, __default_handler
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.weak __irq_dma2_stream1
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.globl __irq_dma2_stream1
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.set __irq_dma2_stream1, __default_handler
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.weak __irq_dma2_stream2
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.globl __irq_dma2_stream2
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.set __irq_dma2_stream2, __default_handler
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.weak __irq_dma2_stream3
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.globl __irq_dma2_stream3
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.set __irq_dma2_stream3, __default_handler
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.weak __irq_dma2_stream4
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.globl __irq_dma2_stream4
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.set __irq_dma2_stream4, __default_handler
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.weak __irq_eth
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.globl __irq_eth
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.set __irq_eth, __default_handler
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.weak __irq_eth_wkup
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.globl __irq_eth_wkup
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.set __irq_eth_wkup, __default_handler
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.weak __irq_can2_tx
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.globl __irq_can2_tx
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.set __irq_can2_tx, __default_handler
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.weak __irq_can2_rx0
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.globl __irq_can2_rx0
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.set __irq_can2_rx0, __default_handler
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.weak __irq_can2_rx1
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.globl __irq_can2_rx1
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.set __irq_can2_rx1, __default_handler
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.weak __irq_can2_sce
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.globl __irq_can2_sce
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.set __irq_can2_sce, __default_handler
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.weak __irq_otg_fs
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.globl __irq_otg_fs
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.set __irq_otg_fs, __default_handler
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.weak __irq_dma2_stream5
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.globl __irq_dma2_stream5
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.set __irq_dma2_stream5, __default_handler
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.weak __irq_dma2_stream6
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.globl __irq_dma2_stream6
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.set __irq_dma2_stream6, __default_handler
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.weak __irq_dma2_stream7
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.globl __irq_dma2_stream7
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.set __irq_dma2_stream7, __default_handler
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.weak __irq_usart6
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.globl __irq_usart6
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.set __irq_usart6, __default_handler
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.weak __irq_i2c3_ev
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.globl __irq_i2c3_ev
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.set __irq_i2c3_ev, __default_handler
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.weak __irq_i2c3_er
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.globl __irq_i2c3_er
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.set __irq_i2c3_er, __default_handler
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.weak __irq_otg_hs_ep1_out
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.globl __irq_otg_hs_ep1_out
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.set __irq_otg_hs_ep1_out, __default_handler
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.weak __irq_otg_hs_ep1_in
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.globl __irq_otg_hs_ep1_in
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.set __irq_otg_hs_ep1_in, __default_handler
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.weak __irq_otg_hs_wkup
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.globl __irq_otg_hs_wkup
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.set __irq_otg_hs_wkup, __default_handler
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.weak __irq_otg_hs
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.globl __irq_otg_hs
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.set __irq_otg_hs, __default_handler
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.weak __irq_dcmi
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.globl __irq_dcmi
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.set __irq_dcmi, __default_handler
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.weak __irq_cryp
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.globl __irq_cryp
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.set __irq_cryp, __default_handler
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.weak __irq_hash_rng
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.globl __irq_hash_rng
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.set __irq_hash_rng, __default_handler
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