50448497f8
Sigh; Emacs's elide-head feature makes it easy to forget to update these. Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
104 lines
3.4 KiB
C
104 lines
3.4 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/nvic.c
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* @brief Nested vector interrupt controller support.
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*/
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#include <libmaple/nvic.h>
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#include <libmaple/scb.h>
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#include <libmaple/stm32.h>
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/**
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* @brief Set interrupt priority for an interrupt line
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*
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* Note: The STM32 only implements 4 bits of priority, ignoring the
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* lower 4 bits. This means there are only 16 levels of priority.
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* Bits[3:0] read as zero and ignore writes.
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*
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* @param irqn device to set
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* @param priority Priority to set, 0 being highest priority and 15
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* being lowest.
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*/
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void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority) {
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if (irqn < 0) {
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/* This interrupt is in the system handler block */
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SCB_BASE->SHP[((uint32)irqn & 0xF) - 4] = (priority & 0xF) << 4;
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} else {
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NVIC_BASE->IP[irqn] = (priority & 0xF) << 4;
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}
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}
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/**
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* @brief Initialize the NVIC, setting interrupts to a default priority.
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*/
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void nvic_init(uint32 address, uint32 offset) {
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uint32 i;
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nvic_set_vector_table(address, offset);
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/*
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* Lower priority level for all peripheral interrupts to lowest
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* possible.
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*/
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for (i = 0; i < STM32_NR_INTERRUPTS; i++) {
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nvic_irq_set_priority((nvic_irq_num)i, 0xF);
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}
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/* Lower systick interrupt priority to lowest level */
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nvic_irq_set_priority(NVIC_SYSTICK, 0xF);
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}
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/**
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* @brief Set the vector table base address.
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*
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* For stand-alone products, the vector table base address is normally
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* the start of Flash (0x08000000).
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*
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* @param address Vector table base address.
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* @param offset Offset from address. Some restrictions apply to the
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* use of nonzero offsets; see the ARM Cortex M3
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* Technical Reference Manual.
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*/
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void nvic_set_vector_table(uint32 address, uint32 offset) {
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SCB_BASE->VTOR = address | (offset & 0x1FFFFF80);
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}
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/**
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* @brief Force a system reset.
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*
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* Resets all major system components, excluding debug.
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*/
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void nvic_sys_reset() {
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uint32 prigroup = SCB_BASE->AIRCR & SCB_AIRCR_PRIGROUP;
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SCB_BASE->AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ | prigroup;
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asm volatile("dsb");
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while (1)
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;
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}
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