152 lines
4.9 KiB
C
152 lines
4.9 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/include/libmaple/syscfg.h
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* @brief System configuration controller (SYSCFG)
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*
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* Availability: STM32F2, STM32F4.
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*/
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#ifndef _LIBMAPLE_SYSCFG_H_
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#define _LIBMAPLE_SYSCFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <libmaple/libmaple_types.h>
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/*
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* Register map and base pointer
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*/
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/**
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* @brief SYSCFG register map type.
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*/
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typedef struct syscfg_reg_map {
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__io uint32 MEMRMP; /**< Memory remap register */
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__io uint32 PMC; /**< Peripheral mode configuration */
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__io uint32 EXTICR[4]; /**< External interrupt configuration registers */
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const uint32 RESERVED1;
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const uint32 RESERVED2;
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__io uint32 CMPCR; /**< Compensation cell control register */
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} syscfg_reg_map;
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/** SYSCFG register map base pointer */
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#define SYSCFG_BASE ((struct syscfg_reg_map*)0x40013800)
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/*
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* Register bit definitions
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*/
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/* Memory remap register */
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#define SYSCFG_MEMRMP_MEM_MODE 0x3
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#define SYSCFG_MEMRMP_MEM_MODE_FLASH 0x0
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#define SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH 0x1
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#define SYSCFG_MEMRMP_MEM_MODE_FSMC_1 0x2
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#define SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM 0x3
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/* Peripheral mode configuration register */
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#define SYSCFG_PMC_MII_RMII_SEL_BIT 23
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#define SYSCFG_PMC_MII_RMII_SEL (1U << SYSCFG_PMC_MII_RMII_SEL_BIT)
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#define SYSCFG_PMC_MII_RMII_SEL_MII (0U << SYSCFG_PMC_MII_RMII_SEL_BIT)
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#define SYSCFG_PMC_MII_RMII_SEL_RMII (1U << SYSCFG_PMC_MII_RMII_SEL_BIT)
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/* External interrupt configuration register 1 */
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#define SYSCFG_EXTICR1_EXTI0 0xF
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#define SYSCFG_EXTICR1_EXTI1 0xF0
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#define SYSCFG_EXTICR1_EXTI2 0xF00
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#define SYSCFG_EXTICR1_EXTI3 0xF000
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/* External interrupt configuration register 2 */
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#define SYSCFG_EXTICR2_EXTI4 0xF
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#define SYSCFG_EXTICR2_EXTI5 0xF0
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#define SYSCFG_EXTICR2_EXTI6 0xF00
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#define SYSCFG_EXTICR2_EXTI7 0xF000
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/* External interrupt configuration register 3 */
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#define SYSCFG_EXTICR3_EXTI8 0xF
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#define SYSCFG_EXTICR3_EXTI9 0xF0
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#define SYSCFG_EXTICR3_EXTI10 0xF00
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#define SYSCFG_EXTICR3_EXTI11 0xF000
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/* External interrupt configuration register 4 */
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#define SYSCFG_EXTICR4_EXTI12 0xF
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#define SYSCFG_EXTICR4_EXTI13 0xF0
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#define SYSCFG_EXTICR4_EXTI14 0xF00
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#define SYSCFG_EXTICR4_EXTI15 0xF000
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/* Compensation cell control register */
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#define SYSCFG_CMPCR_READY_BIT 8
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#define SYSCFG_CMPCR_CMP_PD_BIT 0
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#define SYSCFG_CMPCR_READY (1U << SYSCFG_CMPCR_READY_BIT)
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#define SYSCFG_CMPCR_CMP_PD (1U << SYSCFG_CMPCR_CMP_PD_BIT)
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#define SYSCFG_CMPCR_CMP_PD_PDWN (0U << SYSCFG_CMPCR_CMP_PD_BIT)
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#define SYSCFG_CMPCR_CMP_PD_ENABLE (1U << SYSCFG_CMPCR_CMP_PD_BIT)
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/*
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* Routines
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*/
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void syscfg_init(void);
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void syscfg_enable_io_compensation(void);
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void syscfg_disable_io_compensation(void);
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/**
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* @brief System memory mode
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* These values specify what memory to map to address 0x00000000.
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* @see syscfg_set_mem_mode
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*/
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typedef enum syscfg_mem_mode {
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/** Main flash memory is mapped at 0x0. */
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SYCFG_MEM_MODE_FLASH = SYSCFG_MEMRMP_MEM_MODE_FLASH,
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/** System flash (i.e. ST's baked-in bootloader) is mapped at 0x0. */
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SYCFG_MEM_MODE_SYSTEM_FLASH = SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH,
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/** FSMC bank 1 (NOR/PSRAM 1 and 2) is mapped at 0x0. */
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SYCFG_MEM_MODE_FSMC_BANK_1 = SYSCFG_MEMRMP_MEM_MODE_FSMC_1,
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/** Embedded SRAM (i.e., not backup SRAM) is mapped at 0x0. */
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SYCFG_MEM_MODE_SRAM = SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM,
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} syscfg_mem_mode;
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void syscfg_set_mem_mode(syscfg_mem_mode);
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#ifdef __cplusplus
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}
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#endif
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#endif
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