215 lines
8.2 KiB
C
215 lines
8.2 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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* Copyright (c) 2011-2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/include/libmaple/scb.h
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* @brief System control block header
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*/
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/*
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* FIXME: STM32F2?
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*/
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#ifndef _LIBMAPLE_SCB_H_
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#define _LIBMAPLE_SCB_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <libmaple/libmaple_types.h>
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/*
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* Register map and base pointer
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*/
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/** System control block register map type */
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typedef struct scb_reg_map {
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__io uint32 CPUID; /**< CPU ID Base Register */
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__io uint32 ICSR; /**< Interrupt Control State Register */
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__io uint32 VTOR; /**< Vector Table Offset Register */
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__io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
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__io uint32 SCR; /**< System Control Register */
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__io uint32 CCR; /**< Configuration and Control Register */
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__io uint8 SHP[12]; /**< System Handler Priority Registers
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(4-7, 8-11, 12-15) */
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__io uint32 SHCSR; /**< System Handler Control and State Register */
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__io uint32 CFSR; /**< Configurable Fault Status Register */
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__io uint32 HFSR; /**< Hard Fault Status Register */
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/* DFSR is not documented by ST in PM0056 (as of Revision 4), but
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* there's a 4 byte hole in the SCB register map docs right where
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* it belongs. Since it's specified as "always implemented" in
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* the ARM v7-M ARM, I'm assuming its absence is a bug in the ST
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* doc, but I haven't proven it. [mbolivar] */
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__io uint32 DFSR; /**< Debug Fault Status Register */
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__io uint32 MMFAR; /**< Mem Manage Address Register */
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__io uint32 BFAR; /**< Bus Fault Address Register */
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#if 0
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/* The following registers are implementation-defined according to
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* ARM v7-M, and I can't find evidence of their existence in ST's
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* docs. I'm removing them. Feel free to yell at me if they do
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* exist. [mbolivar]
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*/
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__io uint32 AFSR; /**< Auxiliary Fault Status Register */
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__io uint32 PFR[2]; /**< Processor Feature Register */
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__io uint32 DFR; /**< Debug Feature Register */
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__io uint32 AFR; /**< Auxiliary Feature Register */
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__io uint32 MMFR[4]; /**< Memory Model Feature Register */
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__io uint32 ISAR[5]; /**< ISA Feature Register */
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#endif
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} scb_reg_map;
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/** System control block register map base pointer */
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#define SCB_BASE ((struct scb_reg_map*)0xE000ED00)
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/*
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* Register bit definitions
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*/
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/* No SCB_REG_FIELD_BIT macros as the relevant addresses are not in a
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* bit-band region. */
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/* CPUID base register (SCB_CPUID) */
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#define SCB_CPUID_IMPLEMENTER (0xFF << 24)
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#define SCB_CPUID_VARIANT (0xF << 20)
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#define SCB_CPUID_CONSTANT (0xF << 16)
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#define SCB_CPUID_PARTNO (0xFFF << 4)
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#define SCB_CPUID_REVISION 0xF
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/* Interrupt control state register (SCB_ICSR) */
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#define SCB_ICSR_NMIPENDSET (1U << 31)
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#define SCB_ICSR_PENDSVSET (1U << 28)
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#define SCB_ICSR_PENDSVCLR (1U << 27)
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#define SCB_ICSR_PENDSTSET (1U << 26)
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#define SCB_ICSR_PENDSTCLR (1U << 25)
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#define SCB_ICSR_ISRPENDING (1U << 22)
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#define SCB_ICSR_VECTPENDING (0x3FF << 12)
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#define SCB_ICSR_RETOBASE (1U << 11)
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#define SCB_ICSR_VECTACTIVE 0xFF
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/* Vector table offset register (SCB_VTOR) */
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#define SCB_VTOR_TBLOFF (0x1FFFFF << 9)
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/* Application interrupt and reset control register (SCB_AIRCR) */
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#define SCB_AIRCR_VECTKEYSTAT (0x5FA << 16)
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#define SCB_AIRCR_VECTKEY (0x5FA << 16)
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#define SCB_AIRCR_ENDIANNESS (1U << 15)
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#define SCB_AIRCR_PRIGROUP (0x3 << 8)
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#define SCB_AIRCR_SYSRESETREQ (1U << 2)
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#define SCB_AIRCR_VECTCLRACTIVE (1U << 1)
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#define SCB_AIRCR_VECTRESET (1U << 0)
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/* System control register (SCB_SCR) */
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#define SCB_SCR_SEVONPEND (1U << 4)
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#define SCB_SCR_SLEEPDEEP (1U << 2)
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#define SCB_SCR_SLEEPONEXIT (1U << 1)
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/* Configuration and Control Register (SCB_CCR) */
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#define SCB_CCR_STKALIGN (1U << 9)
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#define SCB_CCR_BFHFNMIGN (1U << 8)
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#define SCB_CCR_DIV_0_TRP (1U << 4)
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#define SCB_CCR_UNALIGN_TRP (1U << 3)
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#define SCB_CCR_USERSETMPEND (1U << 1)
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#define SCB_CCR_NONBASETHRDENA (1U << 0)
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/* System handler priority registers (SCB_SHPRx) */
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#define SCB_SHPR1_PRI6 (0xFF << 16)
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#define SCB_SHPR1_PRI5 (0xFF << 8)
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#define SCB_SHPR1_PRI4 0xFF
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#define SCB_SHPR2_PRI11 (0xFF << 24)
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#define SCB_SHPR3_PRI15 (0xFF << 24)
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#define SCB_SHPR3_PRI14 (0xFF << 16)
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/* System Handler Control and state register (SCB_SHCSR) */
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#define SCB_SHCSR_USGFAULTENA (1U << 18)
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#define SCB_SHCSR_BUSFAULTENA (1U << 17)
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#define SCB_SHCSR_MEMFAULTENA (1U << 16)
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#define SCB_SHCSR_SVCALLPENDED (1U << 15)
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#define SCB_SHCSR_BUSFAULTPENDED (1U << 14)
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#define SCB_SHCSR_MEMFAULTPENDED (1U << 13)
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#define SCB_SHCSR_USGFAULTPENDED (1U << 12)
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#define SCB_SHCSR_SYSTICKACT (1U << 11)
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#define SCB_SHCSR_PENDSVACT (1U << 10)
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#define SCB_SHCSR_MONITORACT (1U << 8)
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#define SCB_SHCSR_SVCALLACT (1U << 7)
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#define SCB_SHCSR_USGFAULTACT (1U << 3)
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#define SCB_SHCSR_BUSFAULTACT (1U << 1)
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#define SCB_SHCSR_MEMFAULTACT (1U << 0)
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/* Configurable fault status register (SCB_CFSR) */
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#define SCB_CFSR_DIVBYZERO (1U << 25)
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#define SCB_CFSR_UNALIGNED (1U << 24)
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#define SCB_CFSR_NOCP (1U << 19)
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#define SCB_CFSR_INVPC (1U << 18)
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#define SCB_CFSR_INVSTATE (1U << 17)
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#define SCB_CFSR_UNDEFINSTR (1U << 16)
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#define SCB_CFSR_BFARVALID (1U << 15)
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#define SCB_CFSR_STKERR (1U << 12)
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#define SCB_CFSR_UNSTKERR (1U << 11)
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#define SCB_CFSR_IMPRECISERR (1U << 10)
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#define SCB_CFSR_PRECISERR (1U << 9)
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#define SCB_CFSR_IBUSERR (1U << 8)
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#define SCB_CFSR_MMARVALID (1U << 7)
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#define SCB_CFSR_MSTKERR (1U << 4)
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#define SCB_CFSR_MUNSTKERR (1U << 3)
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#define SCB_CFSR_DACCVIOL (1U << 1)
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#define SCB_CFSR_IACCVIOL (1U << 0)
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/* Hard Fault Status Register (SCB_HFSR) */
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#define SCB_HFSR_DEBUG_VT (1U << 31)
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#define SCB_CFSR_FORCED (1U << 30)
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#define SCB_CFSR_VECTTBL (1U << 1)
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/* Debug Fault Status Register */
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/* Not specified by PM0056, but required by ARM. The bit definitions
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* here are based on the names given in the ARM v7-M ARM. */
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#define SCB_DFSR_EXTERNAL (1U << 4)
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#define SCB_DFSR_VCATCH (1U << 3)
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#define SCB_DFSR_DWTTRAP (1U << 2)
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#define SCB_DFSR_BKPT (1U << 1)
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#define SCB_DFSR_HALTED (1U << 0)
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#ifdef __cplusplus
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}
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#endif
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#endif
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