414 lines
13 KiB
C
414 lines
13 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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* Copyright (c) 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/include/libmaple/i2c.h
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* @brief Inter-Integrated Circuit (I2C) peripheral support
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*
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* Currently master-only. Usage notes:
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*
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* - Enable an I2C device with i2c_master_enable().
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* - Initialize an array of struct i2c_msg to suit the bus
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* transactions (reads/writes) you wish to perform.
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* - Call i2c_master_xfer() to do the work.
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*/
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#ifndef _LIBMAPLE_I2C_H_
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#define _LIBMAPLE_I2C_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Series header must provide:
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*
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* - uint32 _i2c_bus_clk(i2c_dev*): Clock frequency of dev's bus, in
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* MHz. (This is for internal use only).
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*
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* - (optional) _I2C_HAVE_IRQ_FIXUP: Leave undefined, or define to 1.
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* This is for internal use only. It's a hack to work around a
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* silicon bug related to I2C IRQ pre-emption on some targets. If 1,
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* the series header must also declare and implement a routine with
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* this signature (it may also be provided as a macro):
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*
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* void _i2c_irq_priority_fixup(i2c_dev*)
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*
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* This will be called by i2c_enable_irq() before actually enabling
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* I2C interrupts.
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*
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* - Reg. map base pointers, device pointer declarations.
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*/
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#include <series/i2c.h>
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#include <libmaple/i2c_common.h>
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#include <libmaple/libmaple_types.h>
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#include <libmaple/rcc.h>
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#include <libmaple/nvic.h>
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#include <libmaple/gpio.h>
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/** I2C register map type */
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typedef struct i2c_reg_map {
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__io uint32 CR1; /**< Control register 1 */
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__io uint32 CR2; /**< Control register 2 */
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__io uint32 OAR1; /**< Own address register 1 */
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__io uint32 OAR2; /**< Own address register 2 */
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__io uint32 DR; /**< Data register */
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__io uint32 SR1; /**< Status register 1 */
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__io uint32 SR2; /**< Status register 2 */
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__io uint32 CCR; /**< Clock control register */
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__io uint32 TRISE; /**< TRISE (rise time) register */
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} i2c_reg_map;
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/**
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* @brief I2C message type
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*/
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typedef struct i2c_msg {
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uint16 addr; /**< Address */
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#define I2C_MSG_READ 0x1
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#define I2C_MSG_10BIT_ADDR 0x2
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/**
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* Bitwise OR of:
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* - I2C_MSG_READ (write is default)
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* - I2C_MSG_10BIT_ADDR (7-bit is default) */
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uint16 flags;
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uint16 length; /**< Message length */
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uint16 xferred; /**< Messages transferred */
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uint8 *data; /**< Data */
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} i2c_msg;
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/*
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* Register bit definitions
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*/
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/* Control register 1 */
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#define I2C_CR1_SWRST (1U << 15) // Software reset
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#define I2C_CR1_ALERT (1U << 13) // SMBus alert
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#define I2C_CR1_PEC (1U << 12) // Packet error checking
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#define I2C_CR1_POS (1U << 11) // Acknowledge/PEC position
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#define I2C_CR1_ACK (1U << 10) // Acknowledge enable
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#define I2C_CR1_STOP (1U << 9) // Stop generation
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#define I2C_CR1_START (1U << 8) // Start generation
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#define I2C_CR1_NOSTRETCH (1U << 7) // Clock stretching disable
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#define I2C_CR1_ENGC (1U << 6) // General call enable
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#define I2C_CR1_ENPEC (1U << 5) // PEC enable
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#define I2C_CR1_ENARP (1U << 4) // ARP enable
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#define I2C_CR1_SMBTYPE (1U << 3) // SMBus type
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#define I2C_CR1_SMBTYPE_DEVICE (0U << 3) // SMBus type: device
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#define I2C_CR1_SMBTYPE_HOST (1U << 3) // SMBus type: host
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#define I2C_CR1_SMBUS (1U << 1) // SMBus mode
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#define I2C_CR1_SMBUS_I2C (0U << 1) // SMBus mode: I2C
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#define I2C_CR1_SMBUS_SMBUS (1U << 1) // SMBus mode: SMBus
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#define I2C_CR1_PE (1U << 0) // Peripheral Enable
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/* Control register 2 */
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#define I2C_CR2_LAST (1U << 12) // DMA last transfer
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#define I2C_CR2_DMAEN (1U << 11) // DMA requests enable
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#define I2C_CR2_ITBUFEN (1U << 10) // Buffer interrupt enable
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#define I2C_CR2_ITEVTEN (1U << 9) // Event interupt enable
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#define I2C_CR2_ITERREN (1U << 8) // Error interupt enable
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#define I2C_CR2_FREQ 0x3F // Peripheral input frequency
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/* Own address register 1 */
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#define I2C_OAR1_ADDMODE (1U << 15) // Addressing mode
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#define I2C_OAR1_ADDMODE_7_BIT (0U << 15) // Addressing mode: 7-bit
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#define I2C_OAR1_ADDMODE_10_BIT (1U << 15) // Addressing mode: 10-bit
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#define I2C_OAR1_ADD 0x3FF // Interface address
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/* Own address register 2 */
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#define I2C_OAR2_ADD2 0xFE // Interface address
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#define I2C_OAR2_ENDUAL 1U // Dual addressing mode enable
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/* Status register 1 */
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#define I2C_SR1_SMBALERT (1U << 15) // SMBus alert
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#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error
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#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception
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#define I2C_SR1_OVR (1U << 11) // Overrun/underrun
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#define I2C_SR1_AF (1U << 10) // Acknowledge failure
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#define I2C_SR1_ARLO (1U << 9) // Arbitration lost
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#define I2C_SR1_BERR (1U << 8) // Bus error
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#define I2C_SR1_TXE (1U << 7) // Data register empty
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#define I2C_SR1_RXNE (1U << 6) // Data register not empty
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#define I2C_SR1_STOPF (1U << 4) // Stop detection
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#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent
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#define I2C_SR1_BTF (1U << 2) // Byte transfer finished
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#define I2C_SR1_ADDR (1U << 1) // Address sent/matched
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#define I2C_SR1_SB (1U << 0) // Start bit
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/* Status register 2 */
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#define I2C_SR2_PEC 0xFF00 // Packet error checking register
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#define I2C_SR2_DUALF (1U << 7) // Dual flag
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#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header
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#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address
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#define I2C_SR2_GENCALL (1U << 4) // General call address
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#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver
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#define I2C_SR2_BUSY (1U << 1) // Bus busy
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#define I2C_SR2_MSL (1U << 0) // Master/slave
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/* Clock control register */
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#define I2C_CCR_FS (1U << 15) // Fast mode selection
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#define I2C_CCR_DUTY (1U << 14) // Fast mode duty cycle
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#define I2C_CCR_DUTY_2_1 (0U << 14) // Fast mode duty: 2/1
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#define I2C_CCR_DUTY_16_9 (1U << 14) // Fast mode duty: 16/9
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#define I2C_CCR_CCR 0xFFF // Clock control bits
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/*
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* Convenience routines
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*/
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/* Main I2C API */
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/* I2C enable options */
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#define I2C_FAST_MODE 0x1 // 400 khz
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#define I2C_DUTY_16_9 0x2 // 16/9 duty ratio
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/* Flag 0x4 is reserved; DO NOT USE. */
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#define I2C_BUS_RESET 0x8 // Perform a bus reset
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void i2c_master_enable(i2c_dev *dev, uint32 flags);
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#define I2C_ERROR_PROTOCOL (-1)
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#define I2C_ERROR_TIMEOUT (-2)
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int32 i2c_master_xfer(i2c_dev *dev, i2c_msg *msgs, uint16 num, uint32 timeout);
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void i2c_bus_reset(const i2c_dev *dev);
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/**
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* @brief Disable an I2C device
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*
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* This function disables the corresponding peripheral and marks dev's
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* state as I2C_STATE_DISABLED.
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*
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* @param dev Device to disable.
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*/
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static inline void i2c_disable(i2c_dev *dev) {
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dev->regs->CR1 &= ~I2C_CR1_PE;
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dev->state = I2C_STATE_DISABLED;
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}
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/* Start/stop conditions */
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/**
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* @brief Generate a start condition on the bus.
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* @param dev I2C device
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*/
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static inline void i2c_start_condition(i2c_dev *dev) {
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uint32 cr1;
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while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
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I2C_CR1_STOP |
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I2C_CR1_PEC)) {
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;
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}
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dev->regs->CR1 |= I2C_CR1_START;
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}
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/**
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* @brief Generate a stop condition on the bus
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* @param dev I2C device
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*/
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static inline void i2c_stop_condition(i2c_dev *dev) {
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uint32 cr1;
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while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
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I2C_CR1_STOP |
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I2C_CR1_PEC)) {
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;
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}
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dev->regs->CR1 |= I2C_CR1_STOP;
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while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
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I2C_CR1_STOP |
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I2C_CR1_PEC)) {
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;
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}
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}
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/* IRQ enable/disable */
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#ifndef _I2C_HAVE_IRQ_FIXUP
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/* The series header provides this if _I2C_HAVE_IRQ_FIXUP is defined,
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* but we need it either way. */
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#define _i2c_irq_priority_fixup(dev) ((void)0)
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#endif
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#define I2C_IRQ_ERROR I2C_CR2_ITERREN
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#define I2C_IRQ_EVENT I2C_CR2_ITEVTEN
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#define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN
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/**
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* @brief Enable one or more I2C interrupts
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* @param dev I2C device
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* @param irqs Bitwise or of:
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* I2C_IRQ_ERROR (error interrupt),
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* I2C_IRQ_EVENT (event interrupt), and
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* I2C_IRQ_BUFFER (buffer interrupt).
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*/
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static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) {
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_i2c_irq_priority_fixup(dev);
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dev->regs->CR2 |= irqs;
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}
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/**
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* @brief Disable one or more I2C interrupts
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* @param dev I2C device
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* @param irqs Bitwise or of:
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* I2C_IRQ_ERROR (error interrupt),
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* I2C_IRQ_EVENT (event interrupt), and
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* I2C_IRQ_BUFFER (buffer interrupt).
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*/
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static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) {
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dev->regs->CR2 &= ~irqs;
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}
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/* ACK/NACK */
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/**
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* @brief Enable I2C acknowledgment
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* @param dev I2C device
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*/
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static inline void i2c_enable_ack(i2c_dev *dev) {
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dev->regs->CR1 |= I2C_CR1_ACK;
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}
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/**
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* @brief Disable I2C acknowledgment
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* @param dev I2C device
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*/
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static inline void i2c_disable_ack(i2c_dev *dev) {
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dev->regs->CR1 &= ~I2C_CR1_ACK;
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}
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/* GPIO control */
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/**
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* @brief Configure device GPIOs.
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*
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* Configure GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
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* dev->gpio_port for use with I2C device dev.
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*
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* @param dev I2C Device
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* @see i2c_release_gpios()
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*/
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extern void i2c_config_gpios(const i2c_dev *dev);
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/**
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* @brief Release GPIOs controlling an I2C bus
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*
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* Releases the I2C bus controlled by dev as master, and disconnects
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* GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
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* dev->gpio_port from I2C device dev.
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*
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* @param dev I2C device
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* @see i2c_config_gpios()
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*/
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extern void i2c_master_release_bus(const i2c_dev *dev);
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/* Miscellaneous low-level routines */
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void i2c_init(i2c_dev *dev);
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/**
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* @brief Turn on an I2C peripheral
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* @param dev Device to enable
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*/
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static inline void i2c_peripheral_enable(i2c_dev *dev) {
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dev->regs->CR1 |= I2C_CR1_PE;
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}
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/**
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* @brief Turn off an I2C peripheral
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* @param dev Device to turn off
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*/
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static inline void i2c_peripheral_disable(i2c_dev *dev) {
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dev->regs->CR1 &= ~I2C_CR1_PE;
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}
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/**
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* @brief Fill transmit register
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* @param dev I2C device
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* @param byte Byte to write
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*/
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static inline void i2c_write(i2c_dev *dev, uint8 byte) {
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dev->regs->DR = byte;
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}
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/**
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* @brief Set input clock frequency, in MHz
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* @param dev I2C device
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* @param freq Frequency, in MHz. This must be at least 2, and at most
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* the APB frequency of dev's bus. (For example, if
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* rcc_dev_clk(dev) == RCC_APB1, freq must be at most
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* PCLK1, in MHz). There is an additional limit of 46 MHz.
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*/
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static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) {
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#define I2C_MAX_FREQ_MHZ 46
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ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ);
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uint32 cr2 = dev->regs->CR2;
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cr2 &= ~I2C_CR2_FREQ;
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cr2 |= freq;
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dev->regs->CR2 = freq;
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#undef I2C_MAX_FREQ_MHZ
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}
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/**
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* @brief Set I2C clock control register.
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*
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* See the chip reference manual for the details.
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*
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* @param dev I2C device
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* @param val Value to use for clock control register (in
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* Fast/Standard mode)
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*/
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static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) {
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uint32 ccr = dev->regs->CCR;
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ccr &= ~I2C_CCR_CCR;
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ccr |= val;
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dev->regs->CCR = ccr;
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}
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/**
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* @brief Set SCL rise time
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* @param dev I2C device
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* @param trise Maximum rise time in fast/standard mode (see chip
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* reference manual for the relevant formulas).
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*/
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static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) {
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dev->regs->TRISE = trise;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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