Merge branch 'wip-family-support'

.gitignore

@@ -1,5 +1,6 @@
 build/
-doxygen/
+doxygen/xml/
+doxygen/html/
 main.cpp
 libmaple.layout
 tags

Makefile

@@ -19,10 +19,7 @@ SUPPORT_PATH := $(SRCROOT)/support
 LDDIR := $(SUPPORT_PATH)/ld
 # Support files for this Makefile
 MAKEDIR := $(SUPPORT_PATH)/make
-
-# USB ID for DFU upload
-VENDOR_ID  := 1EAF
-PRODUCT_ID := 0003
+BOARD_INCLUDE_DIR := $(MAKEDIR)/board-includes
 
 ##
 ## Target-specific configuration.  This determines some compiler and
@@ -41,40 +38,42 @@ include $(MAKEDIR)/target-config.mk
 ## Compilation flags
 ##
 
-GLOBAL_FLAGS    := -D$(VECT_BASE_ADDR)					     \
-		   -DBOARD_$(BOARD) -DMCU_$(MCU)			     \
-		   -DERROR_LED_PORT=$(ERROR_LED_PORT)			     \
-		   -DERROR_LED_PIN=$(ERROR_LED_PIN)			     \
-		   -D$(DENSITY)
+# FIXME: the following allows for deprecated include style, e.g.:
+#     #include "libmaple.h"
+# or
+#     #include "wirish.h"
+# It slows compilation noticeably; remove after 1 release.
+TARGET_FLAGS    += -I$(LIBMAPLE_PATH)/include/libmaple                       \
+                   -I$(WIRISH_PATH)/include/wirish
 GLOBAL_CFLAGS   := -Os -g3 -gdwarf-2  -mcpu=cortex-m3 -mthumb -march=armv7-m \
 		   -nostdlib -ffunction-sections -fdata-sections	     \
-		   -Wl,--gc-sections $(GLOBAL_FLAGS)
-GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(GLOBAL_FLAGS)
+		   -Wl,--gc-sections $(TARGET_FLAGS)
+GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(TARGET_FLAGS)
 GLOBAL_ASFLAGS  := -mcpu=cortex-m3 -march=armv7-m -mthumb		     \
-		   -x assembler-with-cpp $(GLOBAL_FLAGS)
-LDFLAGS  = -T$(LDDIR)/$(LDSCRIPT) -L$(LDDIR)    \
-            -mcpu=cortex-m3 -mthumb -Xlinker -L $(LD_FAMILY_PATH)    \
-            -Xlinker --gc-sections -Xlinker --print-gc-sections \
-            -Xassembler --march=armv7-m -Wall
+		   -x assembler-with-cpp $(TARGET_FLAGS)
+LDFLAGS  = $(TARGET_LDFLAGS) -mcpu=cortex-m3 -mthumb \
+           -Xlinker --gc-sections -Xlinker --print-gc-sections \
+           -Xassembler --march=armv7-m -Wall
 ##
 ## Build rules and useful templates
 ##
 
-include $(SUPPORT_PATH)/make/build-rules.mk
-include $(SUPPORT_PATH)/make/build-templates.mk
+include $(MAKEDIR)/build-rules.mk
+include $(MAKEDIR)/build-templates.mk
 
 ##
 ## Set all submodules here
 ##
 
 LIBMAPLE_MODULES += $(SRCROOT)/libmaple
-LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_FAMILY) # family submodule in libmaple
+LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb   # The USB module is kept separate
+LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple
 LIBMAPLE_MODULES += $(SRCROOT)/wirish
+
 # Official libraries:
 LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo
 LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal
 LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire
-
 # Experimental libraries:
 LIBMAPLE_MODULES += $(SRCROOT)/libraries/FreeRTOS
 
@@ -93,16 +92,18 @@ $(foreach m,$(LIBMAPLE_MODULES),$(eval $(call LIBMAPLE_MODULE_template,$(m))))
 # main target
 include $(SRCROOT)/build-targets.mk
 
-.PHONY: install sketch clean help debug cscope tags ctags ram flash jtag doxygen mrproper
+.PHONY: install sketch clean help cscope tags ctags ram flash jtag doxygen mrproper list-boards
 
 # Target upload commands
+# USB ID for DFU upload -- FIXME: do something smarter with this
+BOARD_USB_VENDOR_ID  := 1EAF
+BOARD_USB_PRODUCT_ID := 0003
 UPLOAD_ram   := $(SUPPORT_PATH)/scripts/reset.py && \
                 sleep 1                  && \
-                $(DFU) -a0 -d $(VENDOR_ID):$(PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R
+                $(DFU) -a0 -d $(BOARD_USB_VENDOR_ID):$(BOARD_USB_PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R
 UPLOAD_flash := $(SUPPORT_PATH)/scripts/reset.py && \
                 sleep 1                  && \
-                $(DFU) -a1 -d $(VENDOR_ID):$(PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R
-UPLOAD_jtag  := $(OPENOCD_WRAPPER) flash
+                $(DFU) -a1 -d $(BOARD_USB_VENDOR_ID):$(BOARD_USB_PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R
 
 # Conditionally upload to whatever the last build was
 install: INSTALL_TARGET = $(shell cat $(BUILD_PATH)/build-type 2>/dev/null)
@@ -127,38 +128,37 @@ mrproper: clean
 
 help:
 	@echo ""
-	@echo "  libmaple Makefile help"
-	@echo "  ----------------------"
-	@echo "  "
-	@echo "  Programming targets:"
-	@echo "      sketch:   Compile for BOARD to MEMORY_TARGET (default)."
-	@echo "      install:  Compile and upload code over USB, using Maple bootloader"
-	@echo "  "
-	@echo "  You *must* set BOARD if not compiling for Maple (e.g."
-	@echo "  use BOARD=maple_mini for mini, etc.), and MEMORY_TARGET"
-	@echo "  if not compiling to Flash."
-	@echo "  "
-	@echo "  Valid BOARDs:"
-	@echo "      maple, maple_mini, maple_RET6, maple_native"
-	@echo "  "
-	@echo "  Valid MEMORY_TARGETs (default=flash):"
-	@echo "      ram:    Compile sketch code to ram"
-	@echo "      flash:  Compile sketch code to flash"
-	@echo "      jtag:   Compile sketch code for jtag; overwrites bootloader"
-	@echo "  "
-	@echo "  Other targets:"
-	@echo "      debug:  Start OpenOCD gdb server on port 3333, telnet on port 4444"
-	@echo "      clean: Remove all build and object files"
-	@echo "      help: Show this message"
-	@echo "      doxygen: Build Doxygen HTML and XML documentation"
-	@echo "      mrproper: Remove all generated files"
-	@echo "  "
-
-debug:
-	$(OPENOCD_WRAPPER) debug
+	@echo "Basic usage (BOARD defaults to maple):"
+	@echo "    $$ cp your-main.cpp main.cpp"
+	@echo "    $$ make BOARD=your_board"
+	@echo "    $$ make BOARD=your_board install"
+	@echo ""
+	@echo "(Multiple source files? Link with libmaple.a (\`$$ make library')"
+	@echo "or hack build-targets.mk appropriately.)"
+	@echo ""
+	@echo "Important targets:"
+	@echo "    sketch:   Compile for BOARD to MEMORY_TARGET (default)."
+	@echo "    install:  Compile and upload over USB using Maple bootloader"
+	@echo ""
+	@echo "You *must* set BOARD if not compiling for Maple (e.g."
+	@echo "use BOARD=maple_mini for mini, etc.), and MEMORY_TARGET"
+	@echo "if not compiling to Flash. Run \`$$ make list-boards' for"
+	@echo "a list of all boards."
+	@echo ""
+	@echo "Valid MEMORY_TARGETs (default=flash):"
+	@echo "    ram:    Compile to RAM (doesn't touch Flash)"
+	@echo "    flash:  Compile to Flash (for Maple bootloader)"
+	@echo "    jtag:   Compile for JTAG/SWD upload (overwrites bootloader)"
+	@echo ""
+	@echo "Other targets:"
+	@echo "    clean: Remove all build and object files"
+	@echo "    doxygen: Build Doxygen HTML and XML documentation"
+	@echo "    help: Show this message"
+	@echo "    mrproper: Remove all generated files"
+	@echo ""
 
 cscope:
-	rm -rf *.cscope
+	rm -rf cscope.*
 	find . -name '*.[hcS]' -o -name '*.cpp' | xargs cscope -b
 
 tags:
@@ -180,3 +180,7 @@ jtag:
 
 doxygen:
 	doxygen $(SUPPORT_PATH)/doxygen/Doxyfile
+
+# This output is kind of ugly, but I don't understand make very well.
+list-boards:
+	@echo " $(addsuffix "\\n",$(basename $(notdir $(wildcard $(BOARD_INCLUDE_DIR)/*.mk))))"

README

@@ -122,7 +122,6 @@ Repository Layout
     gdb/              GDB scripts.
     ld/               Linker scripts.
     make/             Additional scripts used by the top-level Makefile.
-    openocd/          OpenOCD scripts for JTAG debugging.
     scripts/          Miscellany.
     doxygen/          Doxygen configuration.
     stm32loader.py    Script for uploading via the built-in USART bootloader.

examples/blinky.cpp

@@ -1,6 +1,6 @@
 // Blinks the built-in LED
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 void setup() {
     pinMode(BOARD_LED_PIN, OUTPUT);

examples/debug-dtrrts.cpp

@@ -1,7 +1,7 @@
 // Test sketch for figuring out DTR/RTS behavior on different platforms.
 
-#include "wirish.h"
-#include "usb.h"
+#include <wirish/wirish.h>
+#include "usb_cdcacm.h"
 
 void setup() {
     /* Set up the LED to blink  */
@@ -10,7 +10,6 @@ void setup() {
     /* Send a message out USART2  */
     Serial2.begin(9600);
     Serial2.println("Debugging DTR/RTS...");
-
 }
 
 void loop() {
@@ -18,9 +17,9 @@ void loop() {
     delay(100);
 
     Serial2.print("DTR: ");
-    Serial2.print(usbGetDTR(), DEC);
+    Serial2.print(usb_cdcacm_get_dtr(), DEC);
     Serial2.print("\tRTS: ");
-    Serial2.println(usbGetRTS(), DEC);
+    Serial2.println(usb_cdcacm_get_rts(), DEC);
 }
 
 // Force init to be called *first*, i.e. before static object allocation.
@@ -32,9 +31,8 @@ __attribute__((constructor)) void premain() {
 int main(void) {
     setup();
 
-    while (1) {
+    while (true) {
         loop();
     }
     return 0;
 }
-

examples/freertos-blinky.cpp

@@ -1,4 +1,4 @@
-#include "wirish.h"
+#include <wirish/wirish.h>
 #include "libraries/FreeRTOS/MapleFreeRTOS.h"
 
 static void vLEDFlashTask(void *pvParameters) {

examples/fsmc-stress-test.cpp

@@ -12,9 +12,9 @@
 #include <stdio.h>
 #include <stddef.h>
 
-#include "wirish.h"
-#include "rcc.h"
-#include "fsmc.h"
+#include <wirish/wirish.h>
+#include <libmaple/rcc.h>
+#include <libmaple/fsmc.h>
 
 // -- SRAM config -------------------------------------------------------------
 

examples/i2c-mcp4725-dac.cpp

@@ -0,0 +1,145 @@
+// i2c-mcp4725-dac.cpp
+//
+// Written by Andrew Meyer <ajm@leaflabs.com>
+// Modified by Marti Bolivar <mbolivar@leaflabs.com>
+//
+// Simple program showing how to control an MCP4725 DAC using the
+// libmaple I2C interface. There's an MCP4725 breakout board available
+// on SparkFun:
+//
+// http://www.sparkfun.com/products/8736
+//
+// How to use:
+//
+// 1. Connect the DAC SDA and SCL pins to I2C2, with a pullup
+//    resistor (1 KOhm should work) to VCC.
+// 2. Load the sketch and connect to SerialUSB.
+// 3. Press the button.
+//
+// The program then makes sure the DAC is connected properly (during
+// setup()), then has the DAC output a sawtooth wave (with loop()).
+
+#include <wirish/wirish.h>
+#include <libmaple/i2c.h>
+
+#define MCP_ADDR         0x60
+#define MCP_WRITE_DAC    0b01000000
+#define MCP_WRITE_EEPROM 0b01100000
+#define MCP_PD_NORMAL    0b00000000
+#define MCP_PD_1K        0b00000010
+#define MCP_PD_100K      0b00000100
+#define MCP_PD_500K      0b00000110
+
+static uint8 write_msg_data[3];
+static i2c_msg write_msg;
+
+static uint8 read_msg_data[5];
+static i2c_msg read_msg;
+
+/*
+ * DAC control routines
+ */
+
+void mcp_i2c_setup(void) {
+    write_msg.addr = MCP_ADDR;
+    write_msg.flags = 0; // write, 7 bit address
+    write_msg.length = sizeof(write_msg_data);
+    write_msg.xferred = 0;
+    write_msg.data = write_msg_data;
+
+    read_msg.addr = MCP_ADDR;
+    read_msg.flags = I2C_MSG_READ;
+    read_msg.length = sizeof(read_msg_data);
+    read_msg.xferred = 0;
+    read_msg.data = read_msg_data;
+}
+
+void mcp_write_val(uint16 val) {
+    write_msg_data[0] = MCP_WRITE_DAC | MCP_PD_NORMAL;
+    uint16 tmp = val >> 4;
+    write_msg_data[1] = tmp;
+    tmp = (val << 4) & 0x00FF;
+    write_msg_data[2] = tmp;
+
+    i2c_master_xfer(I2C2, &write_msg, 1, 0);
+}
+
+uint16 mcp_read_val() {
+    uint16 tmp = 0;
+
+    i2c_master_xfer(I2C2, &read_msg, 1, 2);
+
+    /* We don't care about the status and EEPROM bytes (0, 3, and 4). */
+    tmp = (read_msg_data[1] << 4);
+    tmp += (read_msg_data[2] >> 4);
+    return tmp;
+}
+
+int mcp_test() {
+    uint16 val;
+    uint16 test_val = 0x0101;
+
+    SerialUSB.println("Testing the MCP4725...");
+    /* Read the value of the register (should be 0x0800 if factory fresh) */
+    val = mcp_read_val();
+    SerialUSB.print("DAC Register = 0x");
+    SerialUSB.println(val, HEX);
+
+    mcp_write_val(test_val);
+    SerialUSB.print("Wrote 0x");
+    SerialUSB.print(test_val, HEX);
+    SerialUSB.println(" to the DAC");
+
+    val = mcp_read_val();
+    SerialUSB.print("DAC Register = 0x");
+    SerialUSB.println(val, HEX);
+
+    if (val != test_val) {
+        SerialUSB.println("ERROR: MCP4725 not responding correctly");
+        return 0;
+    }
+
+    SerialUSB.println("MCP4725 seems to be working");
+    return 1;
+}
+
+/*
+ * setup() and loop()
+ */
+
+void setup() {
+    pinMode(BOARD_BUTTON_PIN, INPUT);
+    i2c_master_enable(I2C2, 0);
+    mcp_i2c_setup();
+
+    waitForButtonPress();
+    ASSERT(mcp_test());
+
+    SerialUSB.println("Starting sawtooth wave");
+}
+
+void loop() {
+    static uint16 dout = 0;
+
+    mcp_write_val(dout);
+
+    dout += 50;
+    if (dout >= 32768) {
+        dout = 0;
+    }
+}
+
+// -- init() and main() -------------------------------------------------------
+
+__attribute__((constructor)) void premain() {
+    init();
+}
+
+int main(void) {
+    setup();
+
+    while (true) {
+        loop();
+    }
+    return 0;
+}

examples/mini-exti-test.cpp

@@ -10,7 +10,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 // test routines
 void run_exti_test(void);

examples/qa-slave-shield.cpp

@@ -1,6 +1,6 @@
 // Slave mode for Quality Assurance test
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 #define INTER_TOGGLE_DELAY_NORMAL 5
 #define INTER_TOGGLE_DELAY_SLOW   80

examples/serial-echo.cpp

@@ -0,0 +1,30 @@
+// Simple serial port "echo". Send back any received data.
+
+#include <wirish/wirish.h>
+
+// Note: you can change "Serial1" to any other serial port you have on
+// your board.
+
+void setup() {
+    Serial1.begin(115200);
+}
+
+void loop() {
+    while (Serial1.available()) {
+        Serial1.write(Serial1.read());
+    }
+}
+
+// Force init() to be called before anything else.
+__attribute__((constructor)) void premain() {
+    init();
+}
+
+int main(void) {
+    setup();
+
+    while (true) {
+        loop();
+    }
+    return 0;
+}

examples/spi_master.cpp

@@ -33,7 +33,7 @@
  * Pin 10 is used as slave select.
  */
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 #define NSS 10
 

examples/test-bkp.cpp

@@ -1,8 +1,8 @@
 #include <stdio.h>              // for snprintf()
 
-#include "wirish.h"
-#include "bkp.h"
-#include "iwdg.h"
+#include <wirish/wirish.h>
+#include <libmaple/bkp.h>
+#include <libmaple/iwdg.h>
 
 void print_bkp_contents();
 void write_to_bkp(uint16 val);

examples/test-dac.cpp

@@ -6,8 +6,8 @@
  * This file is released into the public domain.
  */
 
-#include "wirish.h"
-#include "dac.h"
+#include <wirish/wirish.h>
+#include <libmaple/dac.h>
 
 uint16 count = 0;
 

examples/test-fsmc.cpp

@@ -1,7 +1,7 @@
 #include <stddef.h>             // for ptrdiff_t
 
-#include "wirish.h"
-#include "fsmc.h"
+#include <wirish/wirish.h>
+#include <libmaple/fsmc.h>
 
 #ifndef BOARD_maple_native
 #error "Sorry, this example only works on Maple Native."

examples/test-print.cpp

@@ -8,7 +8,7 @@
  * This file is released into the public domain.
  */
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 #undef min
 #undef max
 

examples/test-ring-buffer-insertion.cpp

@@ -12,9 +12,9 @@
  * This file is released into the public domain.
  */
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
-#include "ring_buffer.h"
+#include <libmaple/ring_buffer.h>
 
 #define BUF_SIZE 64
 ring_buffer ring_buf;

examples/test-serial-flush.cpp

@@ -2,7 +2,7 @@
  * Tests the "flush" Serial function.
  */
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 void setup() {
     Serial1.begin(9600);

examples/test-serialusb.cpp

@@ -1,7 +1,7 @@
 // Tests SerialUSB functionality.
 
-#include "wirish.h"
-#include "usb.h"
+#include <wirish/wirish.h>
+#include "usb_cdcacm.h"
 
 #define QUICKPRINT  0
 #define BIGSTUFF    1
@@ -37,7 +37,7 @@ void loop() {
     switch (state) {
         case QUICKPRINT:
             for (int i = 0; i < 30; i++) {
-                usbSendBytes(&c1, 1);
+                usb_cdcacm_putc((char)c1, 1);
                 SerialUSB.print('.');
                 SerialUSB.print('|');
             }

examples/test-servo.cpp

@@ -29,7 +29,7 @@
 
 #include <stdio.h>
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 #include "libraries/Servo/Servo.h"
 

examples/test-session.cpp

@@ -4,7 +4,7 @@
 // Useful for testing Maple features and troubleshooting.
 // Communicates over SerialUSB.
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 // ASCII escape character
 #define ESC       ((uint8)27)

examples/test-spi-roundtrip.cpp

@@ -17,7 +17,7 @@
  * Author: Marti Bolivar <mbolivar@leaflabs.com>
  */
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 HardwareSPI alice(2);
 

examples/test-systick.cpp

@@ -1,7 +1,7 @@
 // Tests the SysTick enable/disable functions
 
-#include "wirish.h"
-#include "systick.h"
+#include <wirish/wirish.h>
+#include <libmaple/systick.h>
 
 void setup() {
     pinMode(BOARD_LED_PIN, OUTPUT);

examples/test-timers.cpp

@@ -1,288 +1,528 @@
-// Program to test the timer.h implementation's essential functionality.
-
-#include "wirish.h"
-#include "timer.h"
-
-void handler1(void);
-void handler2(void);
-void handler3(void);
-void handler4(void);
-
-void handler3b(void);
-void handler4b(void);
-
-int t;
-
-int count1 = 0;
-int count2 = 0;
-int count3 = 0;
-int count4 = 0;
-uint16 rate1 = 1000;
-uint16 rate2 = 2000;
-uint16 rate3 = 4000;
-uint16 rate4 = 8000;
-uint16 val1 = 10000;
-uint16 val2 = 10000;
-uint16 val3 = 10000;
-uint16 val4 = 10000;
-
-// FIXME [0.1.0] high density timer test (especially basic timers + DAC)
-timer_dev *timers[] = {TIMER1, TIMER2, TIMER3, TIMER4};
-voidFuncPtr handlers[] = {handler1, handler2, handler3, handler4};
-
-void initTimer(timer_dev *dev);
-void setTimerPeriod(timer_dev *dev, uint32 period_us);
-void testSetTimerPeriod(uint32 period);
-void testTimerChannels(timer_dev *dev);
-int timerNumber(timer_dev *dev);
+//
+// This is a mostly Wirish-free timer test. Wirish usage is minimized
+// because this is a test of the C timer interface in
+// <libmaple/timer.h>, so it's good if it can be made to work even
+// when most or all of Wirish is missing. Because of that, you may
+// need to customize the following output configuration:
+//
+// Output is printed:
+// - on COMM_USART,
+// - via TX pin on port COMM_USART_PORT, bit COMM_USART_TX_BIT
+// - via RX pin on port COMM_USART_PORT, bit COMM_USART_RX_BIT
+// - at COMM_USART_BAUD baud.
+#define COMM_USART USART6
+#define COMM_USART_BAUD 115200
+#define COMM_USART_PORT GPIOG
+#define COMM_USART_TX_BIT 14
+#define COMM_USART_RX_BIT 9
+// Other optional configuration below.
+
+#include <libmaple/libmaple.h>
+#include <libmaple/gpio.h>
+#include <libmaple/usart.h>
+#include <libmaple/systick.h>
+#include <libmaple/timer.h>
+#include <wirish/boards.h>
+
+//
+// Configuration
+//
+
+// More output if true
+static bool verbose = true;
+
+// Timers to test
+// FIXME use feature test macros for smaller MCUs
+static timer_dev *timers[] = {
+    // Available on all currently supported MCUs
+    TIMER1, TIMER2, TIMER3, TIMER4,
+    // Available on F1 (HD and up), F2
+    TIMER5, TIMER6, TIMER7, TIMER8,
+    // Available on F1 (XL), F2
+    TIMER9, TIMER10, TIMER11, TIMER12, TIMER13, TIMER14,
+};
+
+//
+// Test routines
+//
+
+typedef void (*timer_test_t)(timer_dev *);
+
+static void runTest(const char description[], timer_test_t test);
+static void runTests(void);
+
+static void testGetAndSetCount(timer_dev*);
+static void testPauseAndResume(timer_dev*);
+static void testTimerChannels(timer_dev*);
+
+//
+// Helpers
+//
+
+static void initTimer(timer_dev *dev);
+static int timerNumber(timer_dev *dev);
+// Hack: a systick-based delay, useful until delay_us() is fixed
+static void _delay(uint32 msec);
+// Wirish-less USART initialization routine
+static void init_usart(usart_dev *dev, gpio_dev *gdev, uint8 tx, uint8 rx);
+// Return whether or not the timer has capture/compare channel `ch'.
+// TODO: does something like this belong in the standard timer library?
+static bool timer_has_cc_ch(timer_dev *dev, int ch);
+
+// Printing routines and variants for verbose mode
+static void putstr(const char str[]);
+static void println(void);
+static void putstrln(const char str[]);
+static void putudec(uint32 val);
+static void puttimn(timer_dev *dev);
+static void v_putstr(const char str[]);
+static void v_println();
+static void v_putstrln(const char str[]);
+static void v_putudec(uint32 val);
+static void v_puttimn(timer_dev *dev);
+// Used to visually separate output from different tests
+static void printBanner(void);
+
+//
+// Handler state
+//
+
+static int count1 = 0;
+static int count2 = 0;
+static int count3 = 0;
+static int count4 = 0;
+static int timer_num; // Current timer we're considering
+
+//
+// Timer capture/compare interrupt handlers
+//
+// These are shared between timers. The global variable timer_num
+// controls which timer they affect.
+//
+
+static void handler1(void);
+static void handler2(void);
+static void handler3(void);
+static void handler4(void);
+static voidFuncPtr handlers[] = {handler1, handler2, handler3, handler4};
+
+//
+// setup() and loop()
+//
 
 void setup() {
-    // Set up the LED to blink
-    pinMode(BOARD_LED_PIN, OUTPUT);
-
-    // Setup the button as input
-    pinMode(BOARD_BUTTON_PIN, INPUT);
-
-    // Send a message out Serial2
-    Serial2.begin(115200);
-    Serial2.println("*** Initializing timers...");
+    init_usart(COMM_USART, COMM_USART_PORT,
+               COMM_USART_TX_BIT, COMM_USART_RX_BIT);
+    _delay(5);
+    println();
+    printBanner();
+    putstr("Initializing timers...\r\n");
     timer_foreach(initTimer);
-    Serial2.println("*** Done. Beginning timer test.");
+    putstr("Done. Running tests.\r\n");
+    runTests();
+    printBanner();
+    putstr("Done testing timers.\r\n");
 }
 
 void loop() {
-    Serial2.println("-----------------------------------------------------");
-
-    Serial2.println("Testing timer_get_count()/timer_set_count()");
-    Serial2.print("TIMER1 count = ");
-    Serial2.println(timer_get_count(TIMER1));
-    Serial2.println("timer_set_count(TIMER1, 1234)");
-    timer_set_count(TIMER1, 1234);
-    Serial2.print("timer_get_count(TIMER1) = ");
-    Serial2.println(timer_get_count(TIMER1));
-
-    Serial2.println("-----------------------------------------------------");
-    Serial2.println("Testing pause/resume; button roughly controls TIMER4");
-    // when BUT is held down, TIMER4 is in the "pause" state and the
-    // timer doesn't increment, so the final counts should reflect the
-    // ratio of time that BUT was held down.
-    count3 = 0;
-    count4 = 0;
-    timer_set_mode(TIMER3, TIMER_CH1, TIMER_OUTPUT_COMPARE);
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE);
-    timer_pause(TIMER3);
-    timer_pause(TIMER4);
-    timer_set_count(TIMER3, 0);
-    timer_set_count(TIMER4, 0);
-    timer_set_reload(TIMER3, 30000);
-    timer_set_reload(TIMER4, 30000);
-    timer_set_compare(TIMER3, 1, 1000);
-    timer_set_compare(TIMER4, 1, 1000);
-    timer_attach_interrupt(TIMER3, TIMER_CC1_INTERRUPT, handler3b);
-    timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b);
-    timer_resume(TIMER3);
-    timer_resume(TIMER4);
-
-    Serial2.println("Testing for ~4 seconds...");
-    for(int i = 0; i < 4000; i++) {
-        if (isButtonPressed()) {
-            timer_pause(TIMER4);
-        } else {
-            timer_resume(TIMER4);
-        }
-        delay(1);
-    }
+}
 
-    timer_set_mode(TIMER3, TIMER_CH1, TIMER_DISABLED);
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED);
-
-    Serial2.print("TIMER3 count: ");
-    Serial2.println(timer_get_count(TIMER3));
-    Serial2.print("TIMER4 count: ");
-    Serial2.println(timer_get_count(TIMER4));
-
-    Serial2.println("-----------------------------------------------------");
-    Serial2.println("Testing setTimerPeriod()");
-    testSetTimerPeriod(10);
-    testSetTimerPeriod(30000);
-    testSetTimerPeriod(300000);
-    testSetTimerPeriod(30000);
-
-    Serial2.println("Sanity check (with hand-coded reload and prescaler for "
-                    "72 MHz timers):");
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE);
-    timer_set_prescaler(TIMER4, 33);
-    timer_set_reload(TIMER4, 65454);
-    timer_pause(TIMER4);
-    timer_set_count(TIMER4, 0);
-    timer_set_compare(TIMER4, TIMER_CH1, 1);
-    timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b);
-    Serial2.println("Period 30000ms, wait 2 seconds...");
-    count4 = 0;
-    timer_resume(TIMER4);
-    delay(2000);
-    timer_pause(TIMER4);
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED);
-    Serial2.print("TIMER4 count: ");
-    Serial2.println(count4);
-    Serial2.println("  (Should be around 2sec/30000ms ~ 67)");
-
-    // Test all the individual timer channels
-    timer_foreach(testTimerChannels);
+//
+// Test routine implementations
+//
+
+static void runTests(void) {
+    runTest("timer_get_count()/timer_set_count()", testGetAndSetCount);
+    runTest("timer_pause()/timer_resume()", testPauseAndResume);
+    runTest("capture/compare channels and interrupts",
+            testTimerChannels);
 }
 
-void initTimer(timer_dev *dev) {
-    switch (dev->type) {
-    case TIMER_ADVANCED:
-    case TIMER_GENERAL:
-        Serial2.print("Initializing timer ");
-        Serial2.println(timerNumber(dev));
-        for (int c = 1; c <= 4; c++) {
-            timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE);
-        }
-        Serial2.println("Done.");
-        break;
-    case TIMER_BASIC:
-        break;
+static void runTest(const char description[], timer_test_t test) {
+    printBanner();
+    putstr("Testing ");
+    putstr(description);
+    putstrln(".");
+    timer_foreach(test);
+}
+
+static void testGetAndSetCount(timer_dev *dev) {
+    unsigned before, after;
+    unsigned val_to_set = 1234;
+
+    timer_pause(dev);
+    before = timer_get_count(dev);
+    timer_set_count(dev, val_to_set);
+    after = timer_get_count(dev);
+    timer_resume(dev);
+
+    if (after != val_to_set) {
+        puttimn(dev);
+        putstr(": ");
+        putstr("*** FAIL: get/set count for ");
+        puttimn(dev);
+        putstr(".");
+        putstr("Start count = ");
+        putudec(before);
+        putstr(". Count set to ");
+        putudec(val_to_set);
+        putstr(", and now count is = ");
+        putudec(after);
+        println();
+    } else if (verbose) {
+        puttimn(dev);
+        putstr(": ");
+        putstrln("[ok]");
     }
 }
 
-void testSetTimerPeriod(uint32 period) {
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE);
-    timer_set_compare(TIMER4, TIMER_CH1, 1);
-    setTimerPeriod(TIMER4, period);
-    timer_pause(TIMER4);
-    timer_set_count(TIMER4, 0);
-    timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b);
-    Serial2.println("Period ");
-    Serial2.print(period);
-    Serial2.print(" ms. Waiting 2 seconds...");
-    count4 = 0;
-    timer_resume(TIMER4);
-    delay(2000);
-    timer_pause(TIMER4);
-    timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED);
-    Serial2.print("TIMER4 count: ");
-    Serial2.println(timer_get_count(TIMER4));
-    Serial2.print("  (Should be around 2 sec / ");
-    Serial2.print(period);
-    Serial2.print(" ms = ");
-    Serial2.print(double(2) / period * 1000);
-    Serial2.println(", modulo delays due to interrupts)");
+// This hack works on all currently supported STM32 series, but you
+// may need to do something smarter in the future. The assertions
+// ensure that our assumptions hold for your target.
+static timer_dev *getDifferentTimerOnSameBusAs(timer_dev *dev) {
+    rcc_clk_domain dev_domain = rcc_dev_clk(dev->clk_id);
+    ASSERT(RCC_APB1 == dev_domain || RCC_APB2 == dev_domain);
+    ASSERT(rcc_dev_clk(TIMER1->clk_id) == RCC_APB2);
+    ASSERT(rcc_dev_clk(TIMER2->clk_id) == RCC_APB1);
+    ASSERT(rcc_dev_clk(TIMER8->clk_id) == RCC_APB2);
+    ASSERT(rcc_dev_clk(TIMER3->clk_id) == RCC_APB1);
+
+    if (dev->clk_id == RCC_TIMER1) {
+        return TIMER8;
+    }
+    if (dev->clk_id == RCC_TIMER2) {
+        return TIMER3;
+    }
+    return dev_domain == RCC_APB2 ? TIMER1 : TIMER2;
 }
 
-int timerNumber(timer_dev *dev) {
-    switch (dev->clk_id) {
-    case RCC_TIMER1:
-        return 1;
-    case RCC_TIMER2:
-        return 2;
-    case RCC_TIMER3:
-        return 3;
-    case RCC_TIMER4:
-        return 4;
-#ifdef STM32_HIGH_DENSITY
-    case RCC_TIMER5:
-        return 5;
-    case RCC_TIMER6:
-        return 6;
-    case RCC_TIMER7:
-        return 7;
-    case RCC_TIMER8:
-        return 8;
-#endif
-    default:
-        ASSERT(0);
-        return 0;
+// Rough test of pause and resume.
+//
+// Approximately half the time, dev is in the "pause" state and the
+// timer doesn't increment, while another timer (`base_dev') on the
+// same bus continues. dev and base_dev have identical start counts
+// and prescalers.
+//
+// Since dev and base_dev share a bus (and thus a base clock), and we
+// configure them to have the same prescaler and start count, the
+// ratio of their end counts should be approximately 1 : 2. We check
+// to make sure this is true, up to tolerance `epsilon'.
+static void testPauseAndResume(timer_dev *dev) {
+    timer_dev *base_dev = getDifferentTimerOnSameBusAs(dev);
+    unsigned start_count = 0, reload = 65535;
+    // This prescaler should be enough to ensure that we don't
+    // overflow, while still giving us a reasonably large number of
+    // timer ticks.
+    uint16 prescaler = CYCLES_PER_MICROSECOND * 50;
+    double epsilon = .02;
+
+    if (rcc_dev_clk(base_dev->clk_id) != rcc_dev_clk(dev->clk_id)) {
+        putstrln("*** ERROR: cannot run test. Bus info is messed up.");
+        return;
+    }
+
+    // Pause and set up timers
+    timer_pause(base_dev);
+    timer_pause(dev);
+    timer_set_count(base_dev, start_count);
+    timer_set_count(dev, start_count);
+    timer_set_reload(base_dev, reload);
+    timer_set_reload(dev, reload);
+    timer_set_prescaler(base_dev, prescaler);
+    timer_set_prescaler(dev, prescaler);
+    timer_generate_update(base_dev);
+    timer_generate_update(dev);
+
+    // Resume the timers and run the test
+    ASSERT(timer_get_count(base_dev) == start_count);
+    ASSERT(timer_get_count(dev) == start_count);
+    timer_resume(base_dev);
+    timer_resume(dev);
+    _delay(1000);
+    timer_pause(dev);
+    _delay(1000);
+    timer_pause(base_dev);
+
+    // Check the results
+    unsigned dev_count = timer_get_count(dev);
+    unsigned base_count = timer_get_count(base_dev);
+    double count_ratio = ((double)dev_count / base_count);
+    bool fail = false;
+    if (count_ratio > 0.5 + epsilon || count_ratio < 0.5 - epsilon) {
+        fail = true;
+    }
+    if (fail || verbose) {
+        puttimn(dev);
+        putstr(" vs. ");
+        puttimn(base_dev);
+        putstr(": ");
+        if (fail) putstr("*** FAIL: ");
+        else putstr("[ok] ");
+        putstr("(dev = ");
+        putudec(dev_count);
+        putstr(") / (base = ");
+        putudec(base_count);
+        putstr(") = ");
+        // hack hack hack
+        putudec((int)count_ratio);
+        count_ratio -= (int)count_ratio;
+        putstr(".");
+        int cr_x_100 = (int)(count_ratio * 100);
+        int hundredths = cr_x_100 % 10;
+        cr_x_100 /= 10;
+        int tenths = cr_x_100 % 10;
+        putudec(tenths);
+        putudec(hundredths);
+        println();
     }
 }
 
-/* This function touches every channel of a given timer. The output
- * ratios should reflect the ratios of the rate variables.  It
- * demonstrates that, over time, the actual timing rates get blown
- * away by other system interrupts. */
-void testTimerChannels(timer_dev *dev) {
-    t = timerNumber(dev);
-    toggleLED();
-    delay(100);
-    Serial2.println("-----------------------------------------------------");
+// This function touches every capture/compare channel of a given
+// timer.  The channel counts should be equal within a timer
+// regardless of other interrupts on the system (note that this
+// doesn't really test timers with only a single capture/compare
+// channel; for that, you'll want to do visual inspection of timers
+// that share a bus, in verbose mode).
+static void testTimerChannels(timer_dev *dev) {
     switch (dev->type) {
     case TIMER_BASIC:
-        Serial2.print("NOT testing channels for basic timer ");
-        Serial2.println(t);
-        break;
+        v_putstr("Skipping basic timer ");
+        v_puttimn(dev);
+        v_println();
+        return;
     case TIMER_ADVANCED:
     case TIMER_GENERAL:
-        Serial2.print("Testing channels for timer ");
-        Serial2.println(t);
+        // Set up
+        v_puttimn(dev);
+        v_println();
+        v_putstr("\tchannels: ");
+
+        timer_num = timerNumber(dev);
         timer_pause(dev);
-        count1 = count2 = count3 = count4 = 0;
+        count1 = 0;
+        count2 = 0;
+        count3 = 0;
+        count4 = 0;
         timer_set_reload(dev, 0xFFFF);
         timer_set_prescaler(dev, 1);
         for (int c = 1; c <= 4; c++) {
-            timer_set_compare(dev, c, 65535);
-            timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE);
-            timer_attach_interrupt(dev, c, handlers[c - 1]);
+            if (timer_has_cc_ch(dev, c)) {
+                v_putudec(c);
+                v_putstr("\t");
+                timer_set_compare(dev, c, 0xFFFF);
+                timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE);
+                timer_attach_interrupt(dev, c, handlers[c - 1]);
+            }
         }
+        v_println();
+
+        // Run test
+        timer_generate_update(dev);
         timer_resume(dev);
-        delay(3000);
+        _delay(250);
+        timer_pause(dev);
+
+        // Print results
+        v_putstr("\tcounts:   ");
+        bool fail = false;
+        bool mismatched[4] = {false, false, false, false};
+        int counts[4];
+        counts[0] = count1;
+        counts[1] = count2;
+        counts[2] = count3;
+        counts[3] = count4;
+        bool first = true;
+        int first_count = -1;
+        for (int c = 1; c <= 4; c++) {
+            if (timer_has_cc_ch(dev, c)) {
+                if (first) {
+                    first_count = counts[c - 1];
+                    first = false;
+                }
+                if (!first && (counts[c - 1] != first_count)) {
+                    mismatched[c - 1] = true;
+                    fail = true;
+                }
+                v_putudec(counts[c - 1]);
+                v_putstr("\t");
+            }
+        }
+        v_println();
+        if (fail) {
+            for (int i = 0; i < 4; i++) {
+                if (mismatched[i]) {
+                    putstr("*** FAIL: mismatch on ");
+                    puttimn(dev);
+                    putstr(", channel ");
+                    putudec(i + 1);
+                    putstr(": expected ");
+                    putudec(first_count);
+                    putstr(", got ");
+                    putudec(counts[i]);
+                    println();
+                }
+            }
+        } else {
+            puttimn(dev);
+            putstrln(" [ok]");
+        }
+        v_println();
+
+        // Clean up
         for (int c = 1; c <= 4; c++) {
-            timer_set_mode(dev, c, TIMER_DISABLED);
+            if (timer_has_cc_ch(dev, c)) {
+                timer_set_mode(dev, c, TIMER_DISABLED);
+            }
         }
-        Serial2.print("Channel 1 count: "); Serial2.println(count1);
-        Serial2.print("Channel 2 count: "); Serial2.println(count2);
-        Serial2.print("Channel 3 count: "); Serial2.println(count3);
-        Serial2.print("Channel 4 count: "); Serial2.println(count4);
         break;
     }
 }
 
-// FIXME [0.1.0] move some incarnation of this into timer.h
-void setTimerPeriod(timer_dev *dev, uint32 period_us) {
-    if (!period_us) {
-        // FIXME handle this case
-        ASSERT(0);
-        return;
-    }
+//
+// Helper implementations
+//
 
-    uint32 cycles = period_us * CYCLES_PER_MICROSECOND;
-    uint16 pre = (uint16)((cycles >> 16) + 1);
-    timer_set_prescaler(dev, pre);
-    timer_set_reload(dev, cycles / pre - 1);
+static void _delay(uint32 msec) {
+    uint32 end = systick_uptime() + msec;
+    while (systick_uptime() < end)
+        ;
 }
 
-void handler1(void) {
-    val1 += rate1;
-    timer_set_compare(timers[t], TIMER_CH1, val1);
-    count1++;
+static void init_usart(usart_dev *dev, gpio_dev *gdev, uint8 tx, uint8 rx) {
+    usart_config_gpios_async(dev, gdev, rx, gdev, tx, 0);
+    usart_init(dev);
+    usart_set_baud_rate(dev, USART_USE_PCLK, COMM_USART_BAUD);
+    usart_enable(dev);
 }
 
-void handler2(void) {
-    val2 += rate2;
-    timer_set_compare(timers[t], TIMER_CH2, val2);
-    count2++;
+static bool timer_has_cc_ch(timer_dev *dev, int ch) {
+    ASSERT(1 <= ch && ch <= 4);
+    if (dev->type == TIMER_BASIC)
+        return false;
+    int tn = timerNumber(dev);
+    return  (// TIM1-5 and 8 have all four channels
+             (tn <= 5 || tn == 8) ||
+             // TIM9 and 12 only have channels 1 and 2
+             ((tn == 9 || tn == 12) && ch <= 2) ||
+             // All other general purpose timers only have channel 1
+             (ch == 1));
 }
 
-void handler3(void) {
-    val3 += rate3;
-    timer_set_compare(timers[t], TIMER_CH3, val3);
-    count3++;
+static void putstr(const char str[]) {
+    usart_putstr(COMM_USART, str);
 }
 
-void handler4(void) {
-    val4 += rate4;
-    timer_set_compare(timers[t], TIMER_CH4, val4);
-    count4++;
+static void println(void) {
+    putstr("\r\n");
 }
 
-void handler3b(void) {
+static void putstrln(const char str[]) {
+    putstr(str);
+    println();
+}
+
+static void putudec(uint32 val) {
+    usart_putudec(COMM_USART, val);
+}
+
+static void puttimn(timer_dev *dev) {
+    putstr("TIM");
+    putudec(timerNumber(dev));
+}
+
+static void v_putstr(const char str[]) {
+    if (verbose) putstr(str);
+}
+
+static void v_println() {
+    if (verbose) println();
+}
+
+__attribute__((unused)) /* (shut up, gcc) */
+static void v_putstrln(const char str[]) {
+    if (verbose) putstrln(str);
+}
+
+static void v_putudec(uint32 val) {
+    if (verbose) putudec(val);
+}
+
+static void v_puttimn(timer_dev *dev) {
+    if (verbose) puttimn(dev);
+}
+
+// Used to visually separate output from different tests
+static void printBanner(void) {
+    putstrln("-----------------------------------------------------");
+}
+
+static void initTimer(timer_dev *dev) {
+    v_puttimn(dev);
+    timer_init(dev);
+    switch (dev->type) {
+    case TIMER_ADVANCED:
+    case TIMER_GENERAL:
+        v_putstr(" channels ");
+        for (int c = 1; c <= 4; c++) {
+            if (timer_has_cc_ch(dev, c)) {
+                v_putudec(c);
+                v_putstr(" ");
+                timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE);
+            }
+        }
+        break;
+    case TIMER_BASIC:
+        break;
+    }
+    v_println();
+}
+
+static int timerNumber(timer_dev *dev) {
+    switch (dev->clk_id) {
+    case RCC_TIMER1: return 1;
+    case RCC_TIMER2: return 2;
+    case RCC_TIMER3: return 3;
+    case RCC_TIMER4: return 4;
+    case RCC_TIMER5: return 5;
+    case RCC_TIMER6: return 6;
+    case RCC_TIMER7: return 7;
+    case RCC_TIMER8: return 8;
+    case RCC_TIMER9: return 9;
+    case RCC_TIMER10: return 10;
+    case RCC_TIMER11: return 11;
+    case RCC_TIMER12: return 12;
+    case RCC_TIMER13: return 13;
+    case RCC_TIMER14: return 14;
+    default:
+        ASSERT(0);
+        return 0;
+    }
+}
+
+//
+// IRQ Handlers
+//
+
+static void handler1(void) {
+    count1++;
+}
+
+static void handler2(void) {
+    count2++;
+}
+
+static void handler3(void) {
     count3++;
 }
 
-void handler4b(void) {
+static void handler4(void) {
     count4++;
 }
 
+//
+// init() and main()
+//
+
 __attribute__((constructor)) void premain() {
     init();
 }

examples/test-usart-dma.cpp

@@ -1,5 +1,5 @@
 /**
- * @file test-usart-dma.cpp
+ * @file examples/test-usart-dma.cpp
  * @author Marti Bolivar <mbolivar@leaflabs.com>
  *
  * Simple test of DMA used with a USART receiver.
@@ -12,100 +12,188 @@
  *
  * This example isn't very robust; don't use it in production.  In
  * particular, since the buffer keeps filling (DMA_CIRC_MODE is set),
- * if you keep typing after filling the buffer, you'll overwrite
- * earlier bytes; this may happen before those earlier bytes are done
- * printing.
+ * if you keep sending characters after filling the buffer, you'll
+ * overwrite earlier bytes; this may happen before those earlier bytes
+ * are done printing. (Typing quickly and seeing how it affects the
+ * output is a fun way to make sense of how the interrupts and the
+ * main thread of execution interleave.)
  *
  * This code is released into the public domain.
  */
 
-#include "dma.h"
-#include "usart.h"
-#include "gpio.h"
+#include <libmaple/dma.h>
+#include <libmaple/usart.h>
+#include <libmaple/gpio.h>
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
-#define BAUD 9600
+/*
+ * Configuration and state
+ */
 
-#define USART USART2
-#define USART_HWSER Serial2
+// Serial port and DMA configuration. You can change these to suit
+// your purposes.
+HardwareSerial *serial = &Serial2;
 #define USART_DMA_DEV DMA1
-#define USART_RX_DMA_CHANNEL DMA_CH6
-#define USART_TX BOARD_USART2_TX_PIN
-#define USART_RX BOARD_USART2_RX_PIN
+#if STM32_MCU_SERIES == STM32_SERIES_F1
+// On STM32F1 microcontrollers (like what's on Maple and Maple Mini),
+// dma tubes are channels.
+#define USART_RX_DMA_TUBE DMA_CH6
+#elif (STM32_MCU_SERIES == STM32_SERIES_F2 || \
+       STM32_MCU_SERIES == STM32_SERIES_F4)
+// On STM32F2 and STM32F4 microcontrollers (Maple 2 will have an F4),
+// dma tubes are streams.
+#define USART_RX_DMA_TUBE DMA_S5
+#else
+#error "unsupported stm32 series"
+#endif
+// The serial port will make a DMA request each time it receives data.
+// This is the dma_request_src we use to tell the DMA tube to handle
+// that DMA request.
+#define USART_DMA_REQ_SRC DMA_REQ_SRC_USART2_RX
+#define BAUD 9600
 
-#define BUF_SIZE 8
-uint8 rx_buf[BUF_SIZE];
+// This will store the DMA configuration for USART RX.
+dma_tube_config tube_config;
 
-dma_irq_cause irq_cause;
+// This will store received USART characters.
+#define BUF_SIZE 20
+char rx_buf[BUF_SIZE];
 
+// The interrupt handler, rx_dma_irq(), sets this to 1.
 volatile uint32 irq_fired = 0;
+// Used to store DMA interrupt status register (ISR) bits inside
+// rx_dma_irq(). This helps explain what's going on inside loop(); see
+// comments below.
+volatile uint32 isr = 0;
+
+/*
+ * Helper functions
+ */
+
+// This is our DMA interrupt handler.
+void rx_dma_irq(void) {
+    irq_fired = 1;
+    isr = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE);
+}
+
+// Configure the USART receiver for use with DMA:
+// 1. Turn it on.
+// 2. Set the "DMA request on RX" bit in USART_CR3 (USART_CR3_DMAR).
+void setup_usart(void) {
+    serial->begin(BAUD);
+    usart_dev *serial_dev = serial->c_dev();
+    serial_dev->regs->CR3 = USART_CR3_DMAR;
+}
+
+// Set up our dma_tube_config structure. (We could have done this
+// above, when we declared tube_config, but having this function makes
+// it easier to explain what's going on).
+void setup_tube_config(void) {
+    // We're receiving from the USART data register. serial->c_dev()
+    // returns a pointer to the libmaple usart_dev for that serial
+    // port, so this is a pointer to its data register.
+    tube_config.tube_src = &serial->c_dev()->regs->DR;
+    // We're only interested in the bottom 8 bits of that data register.
+    tube_config.tube_src_size = DMA_SIZE_8BITS;
+    // We're storing to rx_buf.
+    tube_config.tube_dst = rx_buf;
+    // rx_buf is a char array, and a "char" takes up 8 bits on STM32.
+    tube_config.tube_dst_size = DMA_SIZE_8BITS;
+    // Only fill BUF_SIZE - 1 characters, to leave a null byte at the end.
+    tube_config.tube_nr_xfers = BUF_SIZE - 1;
+    // Flags:
+    // - DMA_CFG_DST_INC so we start at the beginning of rx_buf and
+    //   fill towards the end.
+    // - DMA_CFG_CIRC so we go back to the beginning and start over when
+    //   rx_buf fills up.
+    // - DMA_CFG_CMPLT_IE to turn on interrupts on transfer completion.
+    tube_config.tube_flags = DMA_CFG_DST_INC | DMA_CFG_CIRC | DMA_CFG_CMPLT_IE;
+    // Target data: none. It's important to set this to NULL if you
+    // don't have any special (microcontroller-specific) configuration
+    // in mind, which we don't.
+    tube_config.target_data = NULL;
+    // DMA request source.
+    tube_config.tube_req_src = USART_DMA_REQ_SRC;
+}
+
+// Configure the DMA controller to serve DMA requests from the USART.
+void setup_dma_xfer(void) {
+    // First, turn it on.
+    dma_init(USART_DMA_DEV);
+    // Next, configure it by calling dma_tube_cfg(), and check to make
+    // sure it succeeded. DMA tubes have many restrictions on their
+    // configuration, and there are configurations which work on some
+    // types of STM32 but not others. libmaple tries hard to make
+    // things just work, but checking the return status is important!
+    int status = dma_tube_cfg(USART_DMA_DEV, USART_RX_DMA_TUBE, &tube_config);
+    ASSERT(status == DMA_TUBE_CFG_SUCCESS);
+    // Now we'll perform any other configuration we want. For this
+    // example, we attach an interrupt handler.
+    dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_TUBE, rx_dma_irq);
+    // Turn on the DMA tube. It will now begin serving requests.
+    dma_enable(USART_DMA_DEV, USART_RX_DMA_TUBE);
+}
 
-void init_usart(void);
-void init_dma_xfer(void);
-void rx_dma_irq(void);
+/*
+ * setup() and loop()
+ */
 
 void setup(void) {
     pinMode(BOARD_LED_PIN, OUTPUT);
-
-    init_dma_xfer();
-    init_usart();
+    setup_tube_config();
+    setup_dma_xfer();
+    setup_usart();
 }
 
 void loop(void) {
     toggleLED();
     delay(100);
 
-    dma_channel_reg_map *ch_regs = dma_channel_regs(USART_DMA_DEV,
-                                                    USART_RX_DMA_CHANNEL);
+    // See if the interrupt handler got called since the last time we
+    // checked.
     if (irq_fired) {
-        USART_HWSER.println("** IRQ **");
+        serial->println("** IRQ **");
+        // Notice how the interrupt status register (ISR) bits show
+        // transfer complete _and_ half-complete here, but the ISR
+        // bits we print next will be zero. That's because the
+        // variable "isr" gets set _inside_ rx_dma_irq(). After it
+        // exits, libmaple cleans up by clearing the tube's ISR
+        // bits. (If it didn't, and we forgot to, the interrupt would
+        // repeatedly fire forever.)
+        serial->print("ISR bits: 0x");
+        serial->println(isr, HEX);
         irq_fired = 0;
     }
-    USART_HWSER.print("[");
-    USART_HWSER.print(millis());
-    USART_HWSER.print("]\tISR bits: 0x");
-    uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL);
-    USART_HWSER.print(isr_bits, HEX);
-    USART_HWSER.print("\tCCR: 0x");
-    USART_HWSER.print(ch_regs->CCR, HEX);
-    USART_HWSER.print("\tCNDTR: 0x");
-    USART_HWSER.print(ch_regs->CNDTR, HEX);
-    USART_HWSER.print("\tBuffer contents: ");
-     for (int i = 0; i < BUF_SIZE; i++) {
-        USART_HWSER.print('\'');
-        USART_HWSER.print(rx_buf[i]);
-        USART_HWSER.print('\'');
-        if (i < BUF_SIZE - 1) USART_HWSER.print(", ");
-    }
-    USART_HWSER.println();
+
+    // Print the ISR bits.
+    //
+    // Notice that the "transfer half-complete" ISR flag gets set when
+    // we reach the rx_buf half-way point. This is true even though we
+    // don't tell the DMA controller to interrupt us on a
+    // half-complete transfer. That is, the ISR bits get set at the
+    // right times no matter what; we just don't get interrupted
+    // unless we asked. (If an error or other problem occurs, the
+    // relevant ISR bits will get set in the same way).
+    serial->print("[");
+    serial->print(millis());
+    serial->print("]\tISR bits: 0x");
+    uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE);
+    serial->print(isr_bits, HEX);
+
+    // Print the contents of rx_buf. If you keep typing after it fills
+    // up, the new characters will overwrite the old ones, thanks to
+    // DMA_CIRC_MODE.
+    serial->print("\tCharacter buffer contents: '");
+    serial->print(rx_buf);
+    serial->println("'");
     if (isr_bits == 0x7) {
-        USART_HWSER.println("** Clearing ISR bits.");
-        dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL);
+        serial->println("** Clearing ISR bits.");
+        dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE);
     }
 }
 
-/* Configure USART receiver for use with DMA */
-void init_usart(void) {
-    USART_HWSER.begin(BAUD);
-    USART->regs->CR3 = USART_CR3_DMAR;
-}
-
-/* Configure DMA transmission */
-void init_dma_xfer(void) {
-    dma_init(USART_DMA_DEV);
-    dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL,
-                       &USART->regs->DR, DMA_SIZE_8BITS,
-                       rx_buf,           DMA_SIZE_8BITS,
-                       (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT));
-    dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, BUF_SIZE);
-    dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_CHANNEL, rx_dma_irq);
-    dma_enable(USART_DMA_DEV, USART_RX_DMA_CHANNEL);
-}
-
-void rx_dma_irq(void) {
-    irq_fired = true;
-}
+// ------- init() and main() --------------------------------------------------
 
 // Force init to be called *first*, i.e. before static object allocation.
 // Otherwise, statically allocated objects that need libmaple may fail.

examples/vga-leaf.cpp

@@ -32,7 +32,7 @@
 
 // FIXME: generalize for Native and Mini
 
-#include "wirish.h"
+#include <wirish/wirish.h>
 
 // Pinouts -- you also must change the GPIO macros below if you change
 // these

examples/vga-scope.cpp

@@ -35,8 +35,8 @@
   Marti Bolivar <mbolivar@leaflabs.com>
  */
 
-#include "wirish.h"
-#include "systick.h"
+#include <wirish/wirish.h>
+#include <libmaple/systick.h>
 
 // FIXME: generalize for Native and Mini
 

libmaple/adc.c

@@ -25,44 +25,15 @@
  *****************************************************************************/
 
 /**
- * @file adc.c
- *
+ * @file libmaple/adc.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>,
+ *         Perry Hung <perry@leaflabs.com>
  * @brief Analog to digital converter routines
- *
- * IMPORTANT: maximum external impedance must be below 0.4kOhms for 1.5
- * sample conversion time.
- *
- * At 55.5 cycles/sample, the external input impedance < 50kOhms.
- *
- * See STM32 manual RM0008 for how to calculate this.
  */
 
-#include "libmaple.h"
-#include "rcc.h"
-#include "adc.h"
-
-static adc_dev adc1 = {
-    .regs   = ADC1_BASE,
-    .clk_id = RCC_ADC1
-};
-/** ADC1 device. */
-const adc_dev *ADC1 = &adc1;
-
-static adc_dev adc2 = {
-    .regs   = ADC2_BASE,
-    .clk_id = RCC_ADC2
-};
-/** ADC2 device. */
-const adc_dev *ADC2 = &adc2;
-
-#ifdef STM32_HIGH_DENSITY
-adc_dev adc3 = {
-    .regs   = ADC3_BASE,
-    .clk_id = RCC_ADC3
-};
-/** ADC3 device. */
-const adc_dev *ADC3 = &adc3;
-#endif
+#include <libmaple/adc.h>
+#include <libmaple/libmaple.h>
+#include <libmaple/rcc.h>
 
 /**
  * @brief Initialize an ADC peripheral.
@@ -91,20 +62,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) {
 }
 
 /**
- * @brief Call a function on all ADC devices.
- * @param fn Function to call on each ADC device.
- */
-void adc_foreach(void (*fn)(const adc_dev*)) {
-    fn(ADC1);
-    fn(ADC2);
-#ifdef STM32_HIGH_DENSITY
-    fn(ADC3);
-#endif
-}
-
-/**
- * @brief Turn the given sample rate into values for ADC_SMPRx. Don't
- * call this during conversion.
+ * @brief Set the sample rate for all channels on an ADC device.
+ *
+ * Don't call this during conversion.
+ *
  * @param dev adc device
  * @param smp_rate sample rate to set
  * @see adc_smp_rate
@@ -127,25 +88,8 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) {
 }
 
 /**
- * @brief Calibrate an ADC peripheral
- * @param dev adc device
- */
-void adc_calibrate(const adc_dev *dev) {
-    __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
-    __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
-
-    *rstcal_bit = 1;
-    while (*rstcal_bit)
-        ;
-
-    *cal_bit = 1;
-    while (*cal_bit)
-        ;
-}
-
-/**
  * @brief Perform a single synchronous software triggered conversion on a
- * channel.
+ *        channel.
  * @param dev ADC device to use for reading.
  * @param channel channel to convert
  * @return conversion result

libmaple/dac.c

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Bryan Newbold.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,25 +26,20 @@
  *****************************************************************************/
 
 /**
- * @file dac.c
+ * @file libmaple/dac.c
  * @brief Digital to analog converter support.
  */
 
-#include "libmaple.h"
-#include "gpio.h"
-#include "dac.h"
-
-#ifdef STM32_HIGH_DENSITY
-
-/**
- * @brief DAC peripheral routines.
- */
+#include <libmaple/dac.h>
+#include <libmaple/libmaple.h>
+#include <libmaple/gpio.h>
 
+#if STM32_HAVE_DAC
 dac_dev dac = {
     .regs = DAC_BASE,
 };
-/** DAC device. */
 const dac_dev *DAC = &dac;
+#endif
 
 /**
  * @brief Initialize the digital to analog converter
@@ -92,16 +88,16 @@ void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val) {
  */
 void dac_enable_channel(const dac_dev *dev, uint8 channel) {
     /*
-     * Setup ANALOG mode on PA4 and PA5. This mapping is consistent across
-     * all STM32 chips with a DAC. See RM0008 12.2.
+     * Setup ANALOG mode on PA4 and PA5. This mapping is consistent
+     * across all supported STM32s with a DAC.
      */
     switch (channel) {
     case 1:
-        gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG);
+        gpio_set_mode(GPIOA, 4, GPIO_MODE_ANALOG);
         dev->regs->CR |= DAC_CR_EN1;
         break;
     case 2:
-        gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG);
+        gpio_set_mode(GPIOA, 5, GPIO_MODE_ANALOG);
         dev->regs->CR |= DAC_CR_EN2;
         break;
     }
@@ -122,5 +118,3 @@ void dac_disable_channel(const dac_dev *dev, uint8 channel) {
         break;
     }
 }
-
-#endif  /* STM32_HIGH_DENSITY */

libmaple/dac.h

@@ -1,168 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Bryan Newbold.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dac.h
- * @brief Digital to analog converter support.
- */
-
-/* See notes/dac.txt for more info */
-
-#ifndef _DAC_H_
-#define _DAC_H_
-
-#include "rcc.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/** DAC register map. */
-typedef struct dac_reg_map {
-    __io uint32 CR;      /**< Control register */
-    __io uint32 SWTRIGR; /**< Software trigger register */
-    __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8R1;  /**< Channel 1 8-bit left-aligned data
-                              holding register */
-    __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8R2;  /**< Channel 2 8-bit left-aligned data
-                              holding register */
-    __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8RD;  /**< Dual DAC 8-bit right-aligned data holding
-                              register */
-    __io uint32 DOR1;    /**< Channel 1 data output register */
-    __io uint32 DOR2;    /**< Channel 2 data output register */
-} dac_reg_map;
-
-/** DAC register map base address */
-#define DAC_BASE                ((struct dac_reg_map*)0x40007400)
-
-/*
- * Devices
- */
-
-/** DAC device type. */
-typedef struct dac_dev {
-    dac_reg_map *regs; /**< Register map */
-} dac_dev;
-
-extern const dac_dev *DAC;
-
-/*
- * Register bit definitions
- */
-
-/* Control register */
-/* Channel 1 control */
-#define DAC_CR_EN1                   BIT(0) /* Enable */
-#define DAC_CR_BOFF1                 BIT(1) /* Output buffer disable */
-#define DAC_CR_TEN1                  BIT(2) /* Trigger enable */
-#define DAC_CR_TSEL1             (0x7 << 3) /* Trigger selection */
-#define DAC_CR_WAVE1             (0x3 << 6) /* Noise/triangle wave enable */
-#define DAC_CR_MAMP1             (0xF << 8) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN1               BIT(12) /* DMA enable */
-/* Channel 2 control */
-#define DAC_CR_EN2                  BIT(16) /* Enable */
-#define DAC_CR_BOFF2                BIT(17) /* Output buffer disable */
-#define DAC_CR_TEN2                 BIT(18) /* Trigger enable */
-#define DAC_CR_TSEL2            (0x7 << 19) /* Trigger selection */
-#define DAC_CR_WAVE2            (0x3 << 22) /* Noise/triangle wave generation*/
-#define DAC_CR_MAMP2            (0xF << 24) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN2               BIT(28) /* DMA enable */
-
-/* Software trigger register */
-#define DAC_SWTRIGR_SWTRIG1          BIT(0) /* Channel 1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2          BIT(1) /* Channel 2 software trigger */
-
-/* Channel 1 12-bit right-aligned data holding register */
-#define DAC_DHR12R1_DACC1DHR     0x00000FFF
-
-/* Channel 1 12-bit left-aligned data holding register */
-#define DAC_DHR12L1_DACC1DHR     0x0000FFF0
-
-/* Channel 1 8-bit left-aligned data holding register */
-#define DAC_DHR8R1_DACC1DHR      0x000000FF
-
-/* Channel 2 12-bit right-aligned data holding register */
-#define DAC_DHR12R2_DACC2DHR     0x00000FFF
-
-/* Channel 2 12-bit left-aligned data holding register */
-#define DAC_DHR12L2_DACC2DHR     0x0000FFF0
-
-/* Channel 2 8-bit left-aligned data holding register */
-#define DAC_DHR8R2_DACC2DHR      0x000000FF
-
-/* Dual DAC 12-bit right-aligned data holding register */
-#define DAC_DHR12RD_DACC1DHR     0x00000FFF
-#define DAC_DHR12RD_DACC2DHR     0x0FFF0000
-
-/* Dual DAC 12-bit left-aligned data holding register */
-#define DAC_DHR12LD_DACC1DHR     0x0000FFF0
-#define DAC_DHR12LD_DACC2DHR     0xFFF00000
-
-/* Dual DAC 8-bit left-aligned data holding register */
-#define DAC_DHR8RD_DACC1DHR      0x000000FF
-#define DAC_DHR8RD_DACC2DHR      0x0000FF00
-
-/* Channel 1 data output register */
-#define DAC_DOR1_DACC1DOR        0x00000FFF
-
-/* Channel 1 data output register */
-#define DAC_DOR2_DACC2DOR        0x00000FFF
-
-/*
- * Convenience functions
- */
-
-/* We take the dev argument in these convenience functions for
- * future-proofing */
-
-#define DAC_CH1                         0x1
-#define DAC_CH2                         0x2
-void dac_init(const dac_dev *dev, uint32 flags);
-
-void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val);
-void dac_enable_channel(const dac_dev *dev, uint8 channel);
-void dac_disable_channel(const dac_dev *dev, uint8 channel);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif

libmaple/delay.h

@@ -1,30 +0,0 @@
-/**
- * @file delay.h
- * @brief Delay implementation
- */
-
-#include "libmaple_types.h"
-#include "stm32.h"
-
-#ifndef _DELAY_H_
-#define _DELAY_H_
-
-/**
- * @brief Delay the given number of microseconds.
- *
- * @param us Number of microseconds to delay.
- */
-static inline void delay_us(uint32 us) {
-    us *= STM32_DELAY_US_MULT;
-
-    /* fudge for function call overhead  */
-    us--;
-    asm volatile("   mov r0, %[us]          \n\t"
-                 "1: subs r0, #1            \n\t"
-                 "   bhi 1b                 \n\t"
-                 :
-                 : [us] "r" (us)
-                 : "r0");
-}
-#endif
-

libmaple/dma.c

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Michael Hope.
+ * Copyright (c) 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,47 +26,15 @@
  *****************************************************************************/
 
 /**
- * @file dma.c
+ * @file libmaple/dma.c
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
- * @brief Direct Memory Access peripheral support
+ * @brief Portable DMA routines.
  */
 
-#include "dma.h"
-#include "bitband.h"
-#include "util.h"
-
-/*
- * Devices
- */
-
-static dma_dev dma1 = {
-    .regs     = DMA1_BASE,
-    .clk_id   = RCC_DMA1,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH2 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH3 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH4 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH6 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}
-};
-/** DMA1 device */
-dma_dev *DMA1 = &dma1;
-
-#ifdef STM32_HIGH_DENSITY
-static dma_dev dma2 = {
-    .regs     = DMA2_BASE,
-    .clk_id   = RCC_DMA2,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH2   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH3   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */
-};
-/** DMA2 device */
-dma_dev *DMA2 = &dma2;
-#endif
+#include <libmaple/dma.h>
+#include "dma_private.h"
+#include "stm32_private.h"
 
 /*
  * Convenience routines
@@ -79,301 +48,35 @@ void dma_init(dma_dev *dev) {
     rcc_clk_enable(dev->clk_id);
 }
 
-/**
- * @brief Set up a DMA transfer.
- *
- * The channel will be disabled before being reconfigured.  The
- * transfer will have low priority by default.  You may choose another
- * priority before the transfer begins using dma_set_priority(), as
- * well as performing any other configuration you desire.  When the
- * channel is configured to your liking, enable it using dma_enable().
- *
- * @param dev DMA device.
- * @param channel DMA channel.
- * @param peripheral_address Base address of peripheral data register
- *                           involved in the transfer.
- * @param peripheral_size Peripheral data transfer size.
- * @param memory_address Base memory address involved in the transfer.
- * @param memory_size Memory data transfer size.
- * @param mode Logical OR of dma_mode_flags
- * @sideeffect Disables the given DMA channel.
- * @see dma_xfer_size
- * @see dma_mode_flags
- * @see dma_set_num_transfers()
- * @see dma_set_priority()
- * @see dma_attach_interrupt()
- * @see dma_enable()
- */
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode) {
-    dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
-
-    dma_disable(dev, channel);  /* can't write to CMAR/CPAR otherwise */
-    channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
-    channel_regs->CMAR = (uint32)memory_address;
-    channel_regs->CPAR = (uint32)peripheral_address;
-}
-
-/**
- * @brief Set the number of data to be transferred on a DMA channel.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel Channel through which the transfer occurs.
- * @param num_transfers
- */
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers) {
-    dma_channel_reg_map *channel_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    channel_regs->CNDTR = num_transfers;
-}
-
-/**
- * @brief Set the priority of a DMA transfer.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel DMA channel
- * @param priority priority to set.
- */
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority) {
-    dma_channel_reg_map *channel_regs;
-    uint32 ccr;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    ccr = channel_regs->CCR;
-    ccr &= ~DMA_CCR_PL;
-    ccr |= priority;
-    channel_regs->CCR = ccr;
-}
-
-/**
- * @brief Attach an interrupt to a DMA transfer.
- *
- * Interrupts are enabled using appropriate mode flags in
- * dma_setup_transfer().
- *
- * @param dev DMA device
- * @param channel Channel to attach handler to
- * @param handler Interrupt handler to call when channel interrupt fires.
- * @see dma_setup_transfer()
- * @see dma_get_irq_cause()
- * @see dma_detach_interrupt()
- */
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void)) {
-    dev->handlers[channel - 1].handler = handler;
-    nvic_irq_enable(dev->handlers[channel - 1].irq_line);
-}
-
-/**
- * @brief Detach a DMA transfer interrupt handler.
- *
- * After calling this function, the given channel's interrupts will be
- * disabled.
- *
- * @param dev DMA device
- * @param channel Channel whose handler to detach
- * @sideeffect Clears interrupt enable bits in the channel's CCR register.
- * @see dma_attach_interrupt()
- */
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
-    /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
-    dma_channel_regs(dev, channel)->CCR &= ~0xF;
-    dev->handlers[channel - 1].handler = NULL;
-}
-
-/**
- * @brief Discover the reason why a DMA interrupt was called.
- *
- * You may only call this function within an attached interrupt
- * handler for the given channel.
- *
- * This function resets the internal DMA register state which encodes
- * the cause of the interrupt; consequently, it can only be called
- * once per interrupt handler invocation.
- *
- * @param dev DMA device
- * @param channel Channel whose interrupt is being handled.
- * @return Reason why the interrupt fired.
- * @sideeffect Clears channel status flags in dev->regs->ISR.
- * @see dma_attach_interrupt()
- * @see dma_irq_cause
- */
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
-    uint8 status_bits = dma_get_isr_bits(dev, channel);
-
-    /* If the channel global interrupt flag is cleared, then
-     * something's very wrong. */
-    ASSERT(status_bits & BIT(0));
-
-    dma_clear_isr_bits(dev, channel);
-
-    /* ISR flags get set even if the corresponding interrupt enable
-     * bits in the channel's configuration register are cleared, so we
-     * can't use a switch here.
-     *
-     * Don't change the order of these if statements. */
-    if (status_bits & BIT(3)) {
-        return DMA_TRANSFER_ERROR;
-    } else if (status_bits & BIT(1)) {
-        return DMA_TRANSFER_COMPLETE;
-    } else if (status_bits & BIT(2)) {
-        return DMA_TRANSFER_HALF_COMPLETE;
-    } else if (status_bits & BIT(0)) {
-        /* Shouldn't happen (unless someone messed up an IFCR write). */
-        throb();
-    }
-#if DEBUG_LEVEL < DEBUG_ALL
-    else {
-        /* We shouldn't have been called, but the debug level is too
-         * low for the above ASSERT() to have had any effect.  In
-         * order to fail fast, mimic the DMA controller's behavior
-         * when an error occurs. */
-        dma_disable(dev, channel);
-    }
-#endif
-    return DMA_TRANSFER_ERROR;
-}
-
-/**
- * @brief Enable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to enable
- */
-void dma_enable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
-}
-
-/**
- * @brief Disable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to disable
- */
-void dma_disable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
-}
-
-/**
- * @brief Set the base memory address where data will be read from or
- *        written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA memory size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA memory size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose base memory address to set.
- * @param addr Memory base address to use.
- */
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CMAR = (uint32)addr;
-}
-
-/**
- * @brief Set the base peripheral address where data will be read from
- *        or written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA peripheral size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA peripheral size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose peripheral data register base address to set.
- * @param addr Peripheral memory base address to use.
- */
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CPAR = (uint32)addr;
-}
-
 /*
- * IRQ handlers
+ * Private API
  */
 
-static inline void dispatch_handler(dma_dev *dev, dma_channel channel) {
-    void (*handler)(void) = dev->handlers[channel - 1].handler;
-    if (handler) {
-        handler();
-        dma_clear_isr_bits(dev, channel); /* in case handler doesn't */
+enum dma_atype _dma_addr_type(__io void *addr) {
+    switch (stm32_block_purpose((void*)addr)) {
+    /* Notice we're treating the code block as memory here.  That's
+     * correct for addresses in Flash and in [0x0, 0x7FFFFFF]
+     * (provided that those addresses are aliased to Flash, SRAM, or
+     * FSMC, depending on BOOT[01] and possibly SYSCFG_MEMRMP). It's
+     * not correct for other addresses in the code block, but those
+     * will (hopefully) just fail-fast with transfer or bus errors. If
+     * lots of people get confused, it might be worth being more
+     * careful here. */
+    case STM32_BLOCK_CODE:      /* Fall through */
+    case STM32_BLOCK_SRAM:      /* ... */
+    case STM32_BLOCK_FSMC_1_2:  /* ... */
+    case STM32_BLOCK_FSMC_3_4:
+        return DMA_ATYPE_MEM;
+    case STM32_BLOCK_PERIPH:
+        return DMA_ATYPE_PER;
+    case STM32_BLOCK_FSMC_REG:        /* Fall through */
+        /* Is this right? I can't think of a reason to DMA into or out
+         * of the FSMC registers. [mbolivar]  */
+    case STM32_BLOCK_UNUSED:          /* ... */
+    case STM32_BLOCK_CORTEX_INTERNAL: /* ... */
+        return DMA_ATYPE_OTHER;
+    default:
+        ASSERT(0);              /* Can't happen */
+        return DMA_ATYPE_OTHER;
     }
 }
-
-void __irq_dma1_channel1(void) {
-    dispatch_handler(DMA1, DMA_CH1);
-}
-
-void __irq_dma1_channel2(void) {
-    dispatch_handler(DMA1, DMA_CH2);
-}
-
-void __irq_dma1_channel3(void) {
-    dispatch_handler(DMA1, DMA_CH3);
-}
-
-void __irq_dma1_channel4(void) {
-    dispatch_handler(DMA1, DMA_CH4);
-}
-
-void __irq_dma1_channel5(void) {
-    dispatch_handler(DMA1, DMA_CH5);
-}
-
-void __irq_dma1_channel6(void) {
-    dispatch_handler(DMA1, DMA_CH6);
-}
-
-void __irq_dma1_channel7(void) {
-    dispatch_handler(DMA1, DMA_CH7);
-}
-
-#ifdef STM32_HIGH_DENSITY
-void __irq_dma2_channel1(void) {
-    dispatch_handler(DMA2, DMA_CH1);
-}
-
-void __irq_dma2_channel2(void) {
-    dispatch_handler(DMA2, DMA_CH2);
-}
-
-void __irq_dma2_channel3(void) {
-    dispatch_handler(DMA2, DMA_CH3);
-}
-
-void __irq_dma2_channel4_5(void) {
-    dispatch_handler(DMA2, DMA_CH4);
-    dispatch_handler(DMA2, DMA_CH5);
-}
-#endif

libmaple/dma.h

@@ -1,453 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dma.h
- *
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- *
- * @brief Direct Memory Access peripheral support
- */
-
-/*
- * See /notes/dma.txt for more information.
- */
-
-#ifndef _DMA_H_
-#define _DMA_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/**
- * @brief DMA register map type.
- *
- * Note that DMA controller 2 (register map base pointer DMA2_BASE)
- * only supports channels 1--5.
- */
-typedef struct dma_reg_map {
-    __io uint32 ISR;            /**< Interrupt status register */
-    __io uint32 IFCR;           /**< Interrupt flag clear register */
-    __io uint32 CCR1;           /**< Channel 1 configuration register */
-    __io uint32 CNDTR1;         /**< Channel 1 number of data register */
-    __io uint32 CPAR1;          /**< Channel 1 peripheral address register */
-    __io uint32 CMAR1;          /**< Channel 1 memory address register */
-    const uint32 RESERVED1;     /**< Reserved. */
-    __io uint32 CCR2;           /**< Channel 2 configuration register */
-    __io uint32 CNDTR2;         /**< Channel 2 number of data register */
-    __io uint32 CPAR2;          /**< Channel 2 peripheral address register */
-    __io uint32 CMAR2;          /**< Channel 2 memory address register */
-    const uint32 RESERVED2;     /**< Reserved. */
-    __io uint32 CCR3;           /**< Channel 3 configuration register */
-    __io uint32 CNDTR3;         /**< Channel 3 number of data register */
-    __io uint32 CPAR3;          /**< Channel 3 peripheral address register */
-    __io uint32 CMAR3;          /**< Channel 3 memory address register */
-    const uint32 RESERVED3;     /**< Reserved. */
-    __io uint32 CCR4;           /**< Channel 4 configuration register */
-    __io uint32 CNDTR4;         /**< Channel 4 number of data register */
-    __io uint32 CPAR4;          /**< Channel 4 peripheral address register */
-    __io uint32 CMAR4;          /**< Channel 4 memory address register */
-    const uint32 RESERVED4;     /**< Reserved. */
-    __io uint32 CCR5;           /**< Channel 5 configuration register */
-    __io uint32 CNDTR5;         /**< Channel 5 number of data register */
-    __io uint32 CPAR5;          /**< Channel 5 peripheral address register */
-    __io uint32 CMAR5;          /**< Channel 5 memory address register */
-    const uint32 RESERVED5;     /**< Reserved. */
-    __io uint32 CCR6;           /**< Channel 6 configuration register */
-    __io uint32 CNDTR6;         /**< Channel 6 number of data register */
-    __io uint32 CPAR6;          /**< Channel 6 peripheral address register */
-    __io uint32 CMAR6;          /**< Channel 6 memory address register */
-    const uint32 RESERVED6;     /**< Reserved. */
-    __io uint32 CCR7;           /**< Channel 7 configuration register */
-    __io uint32 CNDTR7;         /**< Channel 7 number of data register */
-    __io uint32 CPAR7;          /**< Channel 7 peripheral address register */
-    __io uint32 CMAR7;          /**< Channel 7 memory address register */
-    const uint32 RESERVED7;     /**< Reserved. */
-} dma_reg_map;
-
-/** DMA controller 1 register map base pointer */
-#define DMA1_BASE                       ((struct dma_reg_map*)0x40020000)
-
-#ifdef STM32_HIGH_DENSITY
-/** DMA controller 2 register map base pointer */
-#define DMA2_BASE                       ((struct dma_reg_map*)0x40020400)
-#endif
-
-/*
- * Register bit definitions
- */
-
-/* Interrupt status register */
-
-#define DMA_ISR_TEIF7_BIT               27
-#define DMA_ISR_HTIF7_BIT               26
-#define DMA_ISR_TCIF7_BIT               25
-#define DMA_ISR_GIF7_BIT                24
-#define DMA_ISR_TEIF6_BIT               23
-#define DMA_ISR_HTIF6_BIT               22
-#define DMA_ISR_TCIF6_BIT               21
-#define DMA_ISR_GIF6_BIT                20
-#define DMA_ISR_TEIF5_BIT               19
-#define DMA_ISR_HTIF5_BIT               18
-#define DMA_ISR_TCIF5_BIT               17
-#define DMA_ISR_GIF5_BIT                16
-#define DMA_ISR_TEIF4_BIT               15
-#define DMA_ISR_HTIF4_BIT               14
-#define DMA_ISR_TCIF4_BIT               13
-#define DMA_ISR_GIF4_BIT                12
-#define DMA_ISR_TEIF3_BIT               11
-#define DMA_ISR_HTIF3_BIT               10
-#define DMA_ISR_TCIF3_BIT               9
-#define DMA_ISR_GIF3_BIT                8
-#define DMA_ISR_TEIF2_BIT               7
-#define DMA_ISR_HTIF2_BIT               6
-#define DMA_ISR_TCIF2_BIT               5
-#define DMA_ISR_GIF2_BIT                4
-#define DMA_ISR_TEIF1_BIT               3
-#define DMA_ISR_HTIF1_BIT               2
-#define DMA_ISR_TCIF1_BIT               1
-#define DMA_ISR_GIF1_BIT                0
-
-#define DMA_ISR_TEIF7                   BIT(DMA_ISR_TEIF7_BIT)
-#define DMA_ISR_HTIF7                   BIT(DMA_ISR_HTIF7_BIT)
-#define DMA_ISR_TCIF7                   BIT(DMA_ISR_TCIF7_BIT)
-#define DMA_ISR_GIF7                    BIT(DMA_ISR_GIF7_BIT)
-#define DMA_ISR_TEIF6                   BIT(DMA_ISR_TEIF6_BIT)
-#define DMA_ISR_HTIF6                   BIT(DMA_ISR_HTIF6_BIT)
-#define DMA_ISR_TCIF6                   BIT(DMA_ISR_TCIF6_BIT)
-#define DMA_ISR_GIF6                    BIT(DMA_ISR_GIF6_BIT)
-#define DMA_ISR_TEIF5                   BIT(DMA_ISR_TEIF5_BIT)
-#define DMA_ISR_HTIF5                   BIT(DMA_ISR_HTIF5_BIT)
-#define DMA_ISR_TCIF5                   BIT(DMA_ISR_TCIF5_BIT)
-#define DMA_ISR_GIF5                    BIT(DMA_ISR_GIF5_BIT)
-#define DMA_ISR_TEIF4                   BIT(DMA_ISR_TEIF4_BIT)
-#define DMA_ISR_HTIF4                   BIT(DMA_ISR_HTIF4_BIT)
-#define DMA_ISR_TCIF4                   BIT(DMA_ISR_TCIF4_BIT)
-#define DMA_ISR_GIF4                    BIT(DMA_ISR_GIF4_BIT)
-#define DMA_ISR_TEIF3                   BIT(DMA_ISR_TEIF3_BIT)
-#define DMA_ISR_HTIF3                   BIT(DMA_ISR_HTIF3_BIT)
-#define DMA_ISR_TCIF3                   BIT(DMA_ISR_TCIF3_BIT)
-#define DMA_ISR_GIF3                    BIT(DMA_ISR_GIF3_BIT)
-#define DMA_ISR_TEIF2                   BIT(DMA_ISR_TEIF2_BIT)
-#define DMA_ISR_HTIF2                   BIT(DMA_ISR_HTIF2_BIT)
-#define DMA_ISR_TCIF2                   BIT(DMA_ISR_TCIF2_BIT)
-#define DMA_ISR_GIF2                    BIT(DMA_ISR_GIF2_BIT)
-#define DMA_ISR_TEIF1                   BIT(DMA_ISR_TEIF1_BIT)
-#define DMA_ISR_HTIF1                   BIT(DMA_ISR_HTIF1_BIT)
-#define DMA_ISR_TCIF1                   BIT(DMA_ISR_TCIF1_BIT)
-#define DMA_ISR_GIF1                    BIT(DMA_ISR_GIF1_BIT)
-
-/* Interrupt flag clear register */
-
-#define DMA_IFCR_CTEIF7_BIT             27
-#define DMA_IFCR_CHTIF7_BIT             26
-#define DMA_IFCR_CTCIF7_BIT             25
-#define DMA_IFCR_CGIF7_BIT              24
-#define DMA_IFCR_CTEIF6_BIT             23
-#define DMA_IFCR_CHTIF6_BIT             22
-#define DMA_IFCR_CTCIF6_BIT             21
-#define DMA_IFCR_CGIF6_BIT              20
-#define DMA_IFCR_CTEIF5_BIT             19
-#define DMA_IFCR_CHTIF5_BIT             18
-#define DMA_IFCR_CTCIF5_BIT             17
-#define DMA_IFCR_CGIF5_BIT              16
-#define DMA_IFCR_CTEIF4_BIT             15
-#define DMA_IFCR_CHTIF4_BIT             14
-#define DMA_IFCR_CTCIF4_BIT             13
-#define DMA_IFCR_CGIF4_BIT              12
-#define DMA_IFCR_CTEIF3_BIT             11
-#define DMA_IFCR_CHTIF3_BIT             10
-#define DMA_IFCR_CTCIF3_BIT             9
-#define DMA_IFCR_CGIF3_BIT              8
-#define DMA_IFCR_CTEIF2_BIT             7
-#define DMA_IFCR_CHTIF2_BIT             6
-#define DMA_IFCR_CTCIF2_BIT             5
-#define DMA_IFCR_CGIF2_BIT              4
-#define DMA_IFCR_CTEIF1_BIT             3
-#define DMA_IFCR_CHTIF1_BIT             2
-#define DMA_IFCR_CTCIF1_BIT             1
-#define DMA_IFCR_CGIF1_BIT              0
-
-#define DMA_IFCR_CTEIF7                 BIT(DMA_IFCR_CTEIF7_BIT)
-#define DMA_IFCR_CHTIF7                 BIT(DMA_IFCR_CHTIF7_BIT)
-#define DMA_IFCR_CTCIF7                 BIT(DMA_IFCR_CTCIF7_BIT)
-#define DMA_IFCR_CGIF7                  BIT(DMA_IFCR_CGIF7_BIT)
-#define DMA_IFCR_CTEIF6                 BIT(DMA_IFCR_CTEIF6_BIT)
-#define DMA_IFCR_CHTIF6                 BIT(DMA_IFCR_CHTIF6_BIT)
-#define DMA_IFCR_CTCIF6                 BIT(DMA_IFCR_CTCIF6_BIT)
-#define DMA_IFCR_CGIF6                  BIT(DMA_IFCR_CGIF6_BIT)
-#define DMA_IFCR_CTEIF5                 BIT(DMA_IFCR_CTEIF5_BIT)
-#define DMA_IFCR_CHTIF5                 BIT(DMA_IFCR_CHTIF5_BIT)
-#define DMA_IFCR_CTCIF5                 BIT(DMA_IFCR_CTCIF5_BIT)
-#define DMA_IFCR_CGIF5                  BIT(DMA_IFCR_CGIF5_BIT)
-#define DMA_IFCR_CTEIF4                 BIT(DMA_IFCR_CTEIF4_BIT)
-#define DMA_IFCR_CHTIF4                 BIT(DMA_IFCR_CHTIF4_BIT)
-#define DMA_IFCR_CTCIF4                 BIT(DMA_IFCR_CTCIF4_BIT)
-#define DMA_IFCR_CGIF4                  BIT(DMA_IFCR_CGIF4_BIT)
-#define DMA_IFCR_CTEIF3                 BIT(DMA_IFCR_CTEIF3_BIT)
-#define DMA_IFCR_CHTIF3                 BIT(DMA_IFCR_CHTIF3_BIT)
-#define DMA_IFCR_CTCIF3                 BIT(DMA_IFCR_CTCIF3_BIT)
-#define DMA_IFCR_CGIF3                  BIT(DMA_IFCR_CGIF3_BIT)
-#define DMA_IFCR_CTEIF2                 BIT(DMA_IFCR_CTEIF2_BIT)
-#define DMA_IFCR_CHTIF2                 BIT(DMA_IFCR_CHTIF2_BIT)
-#define DMA_IFCR_CTCIF2                 BIT(DMA_IFCR_CTCIF2_BIT)
-#define DMA_IFCR_CGIF2                  BIT(DMA_IFCR_CGIF2_BIT)
-#define DMA_IFCR_CTEIF1                 BIT(DMA_IFCR_CTEIF1_BIT)
-#define DMA_IFCR_CHTIF1                 BIT(DMA_IFCR_CHTIF1_BIT)
-#define DMA_IFCR_CTCIF1                 BIT(DMA_IFCR_CTCIF1_BIT)
-#define DMA_IFCR_CGIF1                  BIT(DMA_IFCR_CGIF1_BIT)
-
-/* Channel configuration register */
-
-#define DMA_CCR_MEM2MEM_BIT             14
-#define DMA_CCR_MINC_BIT                7
-#define DMA_CCR_PINC_BIT                6
-#define DMA_CCR_CIRC_BIT                5
-#define DMA_CCR_DIR_BIT                 4
-#define DMA_CCR_TEIE_BIT                3
-#define DMA_CCR_HTIE_BIT                2
-#define DMA_CCR_TCIE_BIT                1
-#define DMA_CCR_EN_BIT                  0
-
-#define DMA_CCR_MEM2MEM                 BIT(DMA_CCR_MEM2MEM_BIT)
-#define DMA_CCR_PL                      (0x3 << 12)
-#define DMA_CCR_PL_LOW                  (0x0 << 12)
-#define DMA_CCR_PL_MEDIUM               (0x1 << 12)
-#define DMA_CCR_PL_HIGH                 (0x2 << 12)
-#define DMA_CCR_PL_VERY_HIGH            (0x3 << 12)
-#define DMA_CCR_MSIZE                   (0x3 << 10)
-#define DMA_CCR_MSIZE_8BITS             (0x0 << 10)
-#define DMA_CCR_MSIZE_16BITS            (0x1 << 10)
-#define DMA_CCR_MSIZE_32BITS            (0x2 << 10)
-#define DMA_CCR_PSIZE                   (0x3 << 8)
-#define DMA_CCR_PSIZE_8BITS             (0x0 << 8)
-#define DMA_CCR_PSIZE_16BITS            (0x1 << 8)
-#define DMA_CCR_PSIZE_32BITS            (0x2 << 8)
-#define DMA_CCR_MINC                    BIT(DMA_CCR_MINC_BIT)
-#define DMA_CCR_PINC                    BIT(DMA_CCR_PINC_BIT)
-#define DMA_CCR_CIRC                    BIT(DMA_CCR_CIRC_BIT)
-#define DMA_CCR_DIR                     BIT(DMA_CCR_DIR_BIT)
-#define DMA_CCR_TEIE                    BIT(DMA_CCR_TEIE_BIT)
-#define DMA_CCR_HTIE                    BIT(DMA_CCR_HTIE_BIT)
-#define DMA_CCR_TCIE                    BIT(DMA_CCR_TCIE_BIT)
-#define DMA_CCR_EN                      BIT(DMA_CCR_EN_BIT)
-
-/*
- * Devices
- */
-
-/** Encapsulates state related to a DMA channel interrupt. */
-typedef struct dma_handler_config {
-    void (*handler)(void);      /**< User-specified channel interrupt
-                                     handler */
-    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
-} dma_handler_config;
-
-/** DMA device type */
-typedef struct dma_dev {
-    dma_reg_map *regs;             /**< Register map */
-    rcc_clk_id clk_id;             /**< Clock ID */
-    dma_handler_config handlers[]; /**<
-                                    * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
-                                    * @see dma_detach_interrupt()
-                                    */
-} dma_dev;
-
-extern dma_dev *DMA1;
-#ifdef STM32_HIGH_DENSITY
-extern dma_dev *DMA2;
-#endif
-
-/*
- * Convenience functions
- */
-
-void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
-} dma_mode_flags;
-
-/** Source and destination transfer sizes. */
-typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
-} dma_xfer_size;
-
-/** DMA channel */
-typedef enum dma_channel {
-    DMA_CH1 = 1,                /**< Channel 1 */
-    DMA_CH2 = 2,                /**< Channel 2 */
-    DMA_CH3 = 3,                /**< Channel 3 */
-    DMA_CH4 = 4,                /**< Channel 4 */
-    DMA_CH5 = 5,                /**< Channel 5 */
-    DMA_CH6 = 6,                /**< Channel 6 */
-    DMA_CH7 = 7,                /**< Channel 7 */
-} dma_channel;
-
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode);
-
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers);
-
-/** DMA transfer priority. */
-typedef enum dma_priority {
-    DMA_PRIORITY_LOW       = DMA_CCR_PL_LOW,      /**< Low priority */
-    DMA_PRIORITY_MEDIUM    = DMA_CCR_PL_MEDIUM,   /**< Medium priority */
-    DMA_PRIORITY_HIGH      = DMA_CCR_PL_HIGH,     /**< High priority */
-    DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */
-} dma_priority;
-
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority);
-
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void));
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel);
-
-/**
- * Encodes the reason why a DMA interrupt was called.
- * @see dma_get_irq_cause()
- */
-typedef enum dma_irq_cause {
-    DMA_TRANSFER_COMPLETE,      /**< Transfer is complete. */
-    DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */
-    DMA_TRANSFER_ERROR,         /**< Error occurred during transfer. */
-} dma_irq_cause;
-
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel);
-
-void dma_enable(dma_dev *dev, dma_channel channel);
-void dma_disable(dma_dev *dev, dma_channel channel);
-
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address);
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address);
-
-/**
- * @brief DMA channel register map type.
- *
- * Provides access to an individual channel's registers.
- */
-typedef struct dma_channel_reg_map {
-    __io uint32 CCR;           /**< Channel configuration register */
-    __io uint32 CNDTR;         /**< Channel number of data register */
-    __io uint32 CPAR;          /**< Channel peripheral address register */
-    __io uint32 CMAR;          /**< Channel memory address register */
-} dma_channel_reg_map;
-
-#define DMA_CHANNEL_NREGS 5
-
-/**
- * @brief Obtain a pointer to an individual DMA channel's registers.
- *
- * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1.
- *
- * @param dev DMA device
- * @param channel DMA channel whose channel register map to obtain.
- */
-static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev,
-                                                    dma_channel channel) {
-    __io uint32 *ccr1 = &dev->regs->CCR1;
-    return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1));
-}
-
-/**
- * @brief Check if a DMA channel is enabled
- * @param dev DMA device
- * @param channel Channel whose enabled bit to check.
- */
-static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) {
-    return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN);
-}
-
-/**
- * @brief Get the ISR status bits for a DMA channel.
- *
- * The bits are returned right-aligned, in the following order:
- * transfer error flag, half-transfer flag, transfer complete flag,
- * global interrupt flag.
- *
- * If you're attempting to figure out why a DMA interrupt fired; you
- * may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to return.
- * @see dma_get_irq_cause().
- */
-static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) {
-    uint8 shift = (channel - 1) * 4;
-    return (dev->regs->ISR >> shift) & 0xF;
-}
-
-/**
- * @brief Clear the ISR status bits for a given DMA channel.
- *
- * If you're attempting to clean up after yourself in a DMA interrupt,
- * you may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to clear.
- * @see dma_get_irq_cause()
- */
-static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) {
-    dev->regs->IFCR = BIT(4 * (channel - 1));
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif

libmaple/dma_private.h

@@ -0,0 +1,61 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+#ifndef _LIBMAPLE_DMA_PRIVATE_H_
+#define _LIBMAPLE_DMA_PRIVATE_H_
+
+#include <libmaple/dma.h>
+#include <libmaple/libmaple_types.h>
+
+/*
+ * IRQ handling
+ */
+
+/* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER
+ * in the series support files, which need dma_irq_handler().) */
+#ifdef DMA_GET_HANDLER
+static __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) {
+    void (*handler)(void) = DMA_GET_HANDLER(dev, tube);
+    if (handler) {
+        handler();
+        dma_clear_isr_bits(dev, tube); /* in case handler doesn't */
+    }
+}
+#endif
+
+/*
+ * Conveniences for dealing with tube sources/destinations
+ */
+
+enum dma_atype {
+    DMA_ATYPE_MEM,
+    DMA_ATYPE_PER,
+    DMA_ATYPE_OTHER,
+};
+
+enum dma_atype _dma_addr_type(__io void *addr);
+
+#endif

libmaple/exti.c

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,14 +26,14 @@
  *****************************************************************************/
 
 /**
- * @file exti.c
+ * @file libmaple/exti.c
  * @brief External interrupt control routines
  */
 
-#include "exti.h"
-#include "libmaple.h"
-#include "nvic.h"
-#include "bitband.h"
+#include <libmaple/exti.h>
+#include <libmaple/libmaple.h>
+#include <libmaple/nvic.h>
+#include <libmaple/bitband.h>
 
 static inline void dispatch_single_exti(uint32 exti_num);
 static inline void dispatch_extis(uint32 start, uint32 stop);
@@ -66,7 +67,7 @@ static exti_channel exti_channels[] = {
 };
 
 /*
- * Convenience routines
+ * Portable routines
  */
 
 /**
@@ -80,13 +81,13 @@ static exti_channel exti_channels[] = {
  * @param handler Function handler to execute when interrupt is triggered.
  * @param mode    Type of transition to trigger on, one of:
  *                EXTI_RISING, EXTI_FALLING, EXTI_RISING_FALLING.
- * @see afio_exti_num
- * @see afio_exti_port
+ * @see exti_num
+ * @see exti_cfg
  * @see voidFuncPtr
  * @see exti_trigger_mode
  */
-void exti_attach_interrupt(afio_exti_num num,
-                           afio_exti_port port,
+void exti_attach_interrupt(exti_num num,
+                           exti_cfg port,
                            voidFuncPtr handler,
                            exti_trigger_mode mode) {
     ASSERT(handler);
@@ -108,8 +109,8 @@ void exti_attach_interrupt(afio_exti_num num,
         break;
     }
 
-    /* Map num to port */
-    afio_exti_select(num, port);
+    /* Use the chip-specific exti_select() to map num to port */
+    exti_select(num, port);
 
     /* Unmask external interrupt request */
     bb_peri_set_bit(&EXTI_BASE->IMR, num, 1);
@@ -120,10 +121,10 @@ void exti_attach_interrupt(afio_exti_num num,
 
 /**
  * @brief Unregister an external interrupt handler
- * @param num Number of the external interrupt line to disable.
- * @see afio_exti_num
+ * @param num External interrupt line to disable.
+ * @see exti_num
  */
-void exti_detach_interrupt(afio_exti_num num) {
+void exti_detach_interrupt(exti_num num) {
     /* First, mask the interrupt request */
     bb_peri_set_bit(&EXTI_BASE->IMR, num, 0);
 
@@ -136,27 +137,39 @@ void exti_detach_interrupt(afio_exti_num num) {
 }
 
 /*
+ * Private routines
+ */
+
+void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port) {
+    uint32 shift = 4 * (num % 4);
+    uint32 cr = *exti_cr;
+    cr &= ~(0xF << shift);
+    cr |= port << shift;
+    *exti_cr = cr;
+}
+
+/*
  * Interrupt handlers
  */
 
 void __irq_exti0(void) {
-    dispatch_single_exti(AFIO_EXTI_0);
+    dispatch_single_exti(EXTI0);
 }
 
 void __irq_exti1(void) {
-    dispatch_single_exti(AFIO_EXTI_1);
+    dispatch_single_exti(EXTI1);
 }
 
 void __irq_exti2(void) {
-    dispatch_single_exti(AFIO_EXTI_2);
+    dispatch_single_exti(EXTI2);
 }
 
 void __irq_exti3(void) {
-    dispatch_single_exti(AFIO_EXTI_3);
+    dispatch_single_exti(EXTI3);
 }
 
 void __irq_exti4(void) {
-    dispatch_single_exti(AFIO_EXTI_4);
+    dispatch_single_exti(EXTI4);
 }
 
 void __irq_exti9_5(void) {
@@ -177,7 +190,7 @@ void __irq_exti15_10(void) {
  * won't actually be cleared in time and the ISR will fire again.  To
  * compensate, this function NOPs for 2 cycles after clearing the
  * pending bits to ensure it takes effect. */
-static inline void clear_pending_msk(uint32 exti_msk) {
+static __always_inline void clear_pending_msk(uint32 exti_msk) {
     EXTI_BASE->PR = exti_msk;
     asm volatile("nop");
     asm volatile("nop");
@@ -185,7 +198,7 @@ static inline void clear_pending_msk(uint32 exti_msk) {
 
 /* This dispatch routine is for non-multiplexed EXTI lines only; i.e.,
  * it doesn't check EXTI_PR. */
-static inline void dispatch_single_exti(uint32 exti) {
+static __always_inline void dispatch_single_exti(uint32 exti) {
     voidFuncPtr handler = exti_channels[exti].handler;
 
     if (!handler) {
@@ -193,18 +206,18 @@ static inline void dispatch_single_exti(uint32 exti) {
     }
 
     handler();
-    clear_pending_msk(BIT(exti));
+    clear_pending_msk(1U << exti);
 }
 
 /* Dispatch routine for EXTIs which share an IRQ. */
-static inline void dispatch_extis(uint32 start, uint32 stop) {
+static __always_inline void dispatch_extis(uint32 start, uint32 stop) {
     uint32 pr = EXTI_BASE->PR;
     uint32 handled_msk = 0;
     uint32 exti;
 
     /* Dispatch user handlers for pending EXTIs. */
     for (exti = start; exti <= stop; exti++) {
-        uint32 eb = BIT(exti);
+        uint32 eb = (1U << exti);
         if (pr & eb) {
             voidFuncPtr handler = exti_channels[exti].handler;
             if (handler) {

libmaple/exti_private.h

@@ -0,0 +1,34 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+#ifndef _LIBMAPLE_EXTI_PRIVATE_H_
+#define _LIBMAPLE_EXTI_PRIVATE_H_
+
+#include <libmaple/exti.h>
+
+void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port);
+
+#endif

libmaple/flash.c

@@ -25,30 +25,24 @@
  *****************************************************************************/
 
 /**
- * @file flash.c
+ * @file libmaple/flash.c
  * @brief Flash management functions
  */
 
-#include "libmaple.h"
-#include "flash.h"
-#include "bitband.h"
-
-/**
- * @brief Turn on the hardware prefetcher.
- */
-void flash_enable_prefetch(void) {
-    *bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1;
-}
+#include <libmaple/libmaple_types.h>
+#include <libmaple/flash.h>
 
 /**
  * @brief Set flash wait states
  *
- * See ST PM0042, section 3.1 for restrictions on the acceptable value
- * of wait_states for a given SYSCLK configuration.
+ * Note that not all wait states are available on every MCU. See the
+ * Flash programming manual for your MCU for restrictions on the
+ * allowed value of wait_states for a given system clock (SYSCLK)
+ * frequency.
  *
  * @param wait_states number of wait states (one of
  *                    FLASH_WAIT_STATE_0, FLASH_WAIT_STATE_1,
- *                    FLASH_WAIT_STATE_2).
+ *                    ..., FLASH_WAIT_STATE_7).
  */
 void flash_set_latency(uint32 wait_states) {
     uint32 val = FLASH_BASE->ACR;

libmaple/gpio.c

@@ -25,77 +25,15 @@
  *****************************************************************************/
 
 /**
- * @file gpio.c
- * @brief GPIO initialization routine
+ * @file libmaple/gpio.c
+ * @brief Generic STM32 GPIO support.
  */
 
-#include "gpio.h"
-#include "rcc.h"
+#include <libmaple/gpio.h>
+#include <libmaple/rcc.h>
 
 /*
- * GPIO devices
- */
-
-gpio_dev gpioa = {
-    .regs      = GPIOA_BASE,
-    .clk_id    = RCC_GPIOA,
-    .exti_port = AFIO_EXTI_PA,
-};
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
-
-gpio_dev gpiob = {
-    .regs      = GPIOB_BASE,
-    .clk_id    = RCC_GPIOB,
-    .exti_port = AFIO_EXTI_PB,
-};
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
-
-gpio_dev gpioc = {
-    .regs      = GPIOC_BASE,
-    .clk_id    = RCC_GPIOC,
-    .exti_port = AFIO_EXTI_PC,
-};
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
-
-gpio_dev gpiod = {
-    .regs      = GPIOD_BASE,
-    .clk_id    = RCC_GPIOD,
-    .exti_port = AFIO_EXTI_PD,
-};
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
-
-#ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
-    .regs      = GPIOE_BASE,
-    .clk_id    = RCC_GPIOE,
-    .exti_port = AFIO_EXTI_PE,
-};
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
-
-gpio_dev gpiof = {
-    .regs      = GPIOF_BASE,
-    .clk_id    = RCC_GPIOF,
-    .exti_port = AFIO_EXTI_PF,
-};
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
-
-gpio_dev gpiog = {
-    .regs      = GPIOG_BASE,
-    .clk_id    = RCC_GPIOG,
-    .exti_port = AFIO_EXTI_PG,
-};
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
-#endif
-
-/*
- * GPIO convenience routines
+ * GPIO routines
  */
 
 /**
@@ -109,88 +47,3 @@ void gpio_init(gpio_dev *dev) {
     rcc_clk_enable(dev->clk_id);
     rcc_reset_dev(dev->clk_id);
 }
-
-/**
- * Initialize and reset all available GPIO devices.
- */
-void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
-#ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
-#endif
-}
-
-/**
- * Set the mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode General purpose or alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
-    __io uint32 *cr = &regs->CRL + (pin >> 3);
-    uint32 shift = (pin & 0x7) * 4;
-    uint32 tmp = *cr;
-
-    tmp &= ~(0xF << shift);
-    tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift;
-    *cr = tmp;
-
-    if (mode == GPIO_INPUT_PD) {
-        regs->ODR &= ~BIT(pin);
-    } else if (mode == GPIO_INPUT_PU) {
-        regs->ODR |= BIT(pin);
-    }
-}
-
-/*
- * AFIO
- */
-
-/**
- * @brief Initialize the AFIO clock, and reset the AFIO registers.
- */
-void afio_init(void) {
-    rcc_clk_enable(RCC_AFIO);
-    rcc_reset_dev(RCC_AFIO);
-}
-
-#define AFIO_EXTI_SEL_MASK 0xF
-
-/**
- * @brief Select a source input for an external interrupt.
- *
- * @param exti      External interrupt.
- * @param gpio_port Port which contains pin to use as source input.
- * @see afio_exti_num
- * @see afio_exti_port
- */
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
-    __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4;
-    uint32 shift = 4 * (exti % 4);
-    uint32 cr = *exti_cr;
-
-    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
-    cr |= gpio_port << shift;
-    *exti_cr = cr;
-}
-
-/**
- * @brief Perform an alternate function remap.
- * @param remapping Remapping to perform.
- */
-void afio_remap(afio_remap_peripheral remapping) {
-    if (remapping & AFIO_REMAP_USE_MAPR2) {
-        remapping &= ~AFIO_REMAP_USE_MAPR2;
-        AFIO_BASE->MAPR2 |= remapping;
-    } else {
-        AFIO_BASE->MAPR |= remapping;
-    }
-}

libmaple/i2c.c

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,49 +26,28 @@
  *****************************************************************************/
 
 /**
- * @file i2c.c
+ * @file libmaple/i2c.c
+ * @author Perry Hung <perry@leaflabs.com>
  * @brief Inter-Integrated Circuit (I2C) support.
  *
  * Currently, only master mode is supported.
  */
 
-#include "libmaple.h"
-#include "rcc.h"
-#include "gpio.h"
-#include "nvic.h"
-#include "i2c.h"
-#include "string.h"
-#include "systick.h"
-
-static i2c_dev i2c_dev1 = {
-    .regs         = I2C1_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 7,
-    .scl_pin      = 6,
-    .clk_id       = RCC_I2C1,
-    .ev_nvic_line = NVIC_I2C1_EV,
-    .er_nvic_line = NVIC_I2C1_ER,
-    .state        = I2C_STATE_DISABLED
-};
-/** I2C1 device */
-i2c_dev* const I2C1 = &i2c_dev1;
-
-static i2c_dev i2c_dev2 = {
-    .regs         = I2C2_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 11,
-    .scl_pin      = 10,
-    .clk_id       = RCC_I2C2,
-    .ev_nvic_line = NVIC_I2C2_EV,
-    .er_nvic_line = NVIC_I2C2_ER,
-    .state        = I2C_STATE_DISABLED
-};
-/** I2C2 device */
-i2c_dev* const I2C2 = &i2c_dev2;
+#include "i2c_private.h"
+
+#include <libmaple/libmaple.h>
+#include <libmaple/rcc.h>
+#include <libmaple/gpio.h>
+#include <libmaple/nvic.h>
+#include <libmaple/i2c.h>
+#include <libmaple/systick.h>
+
+#include <string.h>
 
 static inline int32 wait_for_state_change(i2c_dev *dev,
                                           i2c_state state,
                                           uint32 timeout);
+static void set_ccr_trise(i2c_dev *dev, uint32 flags);
 
 /**
  * @brief Fill data register with slave address
@@ -125,10 +105,191 @@ enum {
 };
 
 /**
- * @brief IRQ handler for I2C master. Handles transmission/reception.
+ * @brief Reset an I2C bus.
+ *
+ * Reset is accomplished by clocking out pulses until any hung slaves
+ * release SDA and SCL, then generating a START condition, then a STOP
+ * condition.
+ *
+ * @param dev I2C device
+ */
+void i2c_bus_reset(const i2c_dev *dev) {
+    /* Release both lines */
+    i2c_master_release_bus(dev);
+
+    /*
+     * Make sure the bus is free by clocking it until any slaves release the
+     * bus.
+     */
+    while (!gpio_read_bit(sda_port(dev), dev->sda_pin)) {
+        /* Wait for any clock stretching to finish */
+        while (!gpio_read_bit(scl_port(dev), dev->scl_pin))
+            ;
+        delay_us(10);
+
+        /* Pull low */
+        gpio_write_bit(scl_port(dev), dev->scl_pin, 0);
+        delay_us(10);
+
+        /* Release high again */
+        gpio_write_bit(scl_port(dev), dev->scl_pin, 1);
+        delay_us(10);
+    }
+
+    /* Generate start then stop condition */
+    gpio_write_bit(sda_port(dev), dev->sda_pin, 0);
+    delay_us(10);
+    gpio_write_bit(scl_port(dev), dev->scl_pin, 0);
+    delay_us(10);
+    gpio_write_bit(scl_port(dev), dev->scl_pin, 1);
+    delay_us(10);
+    gpio_write_bit(sda_port(dev), dev->sda_pin, 1);
+}
+
+/**
+ * @brief Initialize an I2C device and reset its registers to their
+ *        default values.
+ * @param dev Device to initialize.
+ */
+void i2c_init(i2c_dev *dev) {
+    rcc_reset_dev(dev->clk_id);
+    rcc_clk_enable(dev->clk_id);
+}
+
+/* Hack for deprecated bit of STM32F1 functionality */
+#ifndef _I2C_HAVE_DEPRECATED_I2C_REMAP
+#define _i2c_handle_remap(dev, flags) ((void)0)
+#endif
+
+/**
+ * @brief Initialize an I2C device as bus master
+ * @param dev Device to enable
+ * @param flags Bitwise or of the following I2C options:
+ *              I2C_FAST_MODE: 400 khz operation,
+ *              I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
+ *                             fast mode),
+ *              I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
+ *                             initialization,
+ *              I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
+ *              I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
+ *                         SDA/PB9.
+ */
+void i2c_master_enable(i2c_dev *dev, uint32 flags) {
+    /* PE must be disabled to configure the device */
+    ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
+
+    /* Ugh */
+    _i2c_handle_remap(dev, flags);
+
+    /* Reset the bus. Clock out any hung slaves. */
+    if (flags & I2C_BUS_RESET) {
+        i2c_bus_reset(dev);
+    }
+
+    /* Turn on clock and set GPIO modes */
+    i2c_init(dev);
+    i2c_config_gpios(dev);
+
+    /* Configure clock and rise time */
+    set_ccr_trise(dev, flags);
+
+    /* Enable event and buffer interrupts */
+    nvic_irq_enable(dev->ev_nvic_line);
+    nvic_irq_enable(dev->er_nvic_line);
+    i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
+
+    /* Make it go! */
+    i2c_peripheral_enable(dev);
+
+    dev->state = I2C_STATE_IDLE;
+}
+
+/**
+ * @brief Process an i2c transaction.
+ *
+ * Transactions are composed of one or more i2c_msg's, and may be read
+ * or write tranfers.  Multiple i2c_msg's will generate a repeated
+ * start in between messages.
+ *
  * @param dev I2C device
+ * @param msgs Messages to send/receive
+ * @param num Number of messages to send/receive
+ * @param timeout Bus idle timeout in milliseconds before aborting the
+ *                transfer.  0 denotes no timeout.
+ * @return 0 on success,
+ *         I2C_ERROR_PROTOCOL if there was a protocol error,
+ *         I2C_ERROR_TIMEOUT if the transfer timed out.
  */
-static void i2c_irq_handler(i2c_dev *dev) {
+int32 i2c_master_xfer(i2c_dev *dev,
+                      i2c_msg *msgs,
+                      uint16 num,
+                      uint32 timeout) {
+    int32 rc;
+
+    ASSERT(dev->state == I2C_STATE_IDLE);
+
+    dev->msg = msgs;
+    dev->msgs_left = num;
+    dev->timestamp = systick_uptime();
+    dev->state = I2C_STATE_BUSY;
+
+    i2c_enable_irq(dev, I2C_IRQ_EVENT);
+    i2c_start_condition(dev);
+
+    rc = wait_for_state_change(dev, I2C_STATE_XFER_DONE, timeout);
+    if (rc < 0) {
+        goto out;
+    }
+
+    dev->state = I2C_STATE_IDLE;
+out:
+    return rc;
+}
+
+/**
+ * @brief Wait for an I2C event, or time out in case of error.
+ * @param dev I2C device
+ * @param state I2C_state state to wait for
+ * @param timeout Timeout, in milliseconds
+ * @return 0 if target state is reached, a negative value on error.
+ */
+static inline int32 wait_for_state_change(i2c_dev *dev,
+                                          i2c_state state,
+                                          uint32 timeout) {
+    i2c_state tmp;
+
+    while (1) {
+        tmp = dev->state;
+
+        if (tmp == I2C_STATE_ERROR) {
+            return I2C_STATE_ERROR;
+        }
+
+        if (tmp == state) {
+            return 0;
+        }
+
+        if (timeout) {
+            if (systick_uptime() > (dev->timestamp + timeout)) {
+                /* TODO: overflow? */
+                /* TODO: racy? */
+                return I2C_ERROR_TIMEOUT;
+            }
+        }
+    }
+}
+
+/*
+ * Private API
+ */
+
+/*
+ * IRQ handler for I2C master. Handles transmission/reception.
+ */
+void _i2c_irq_handler(i2c_dev *dev) {
+    /* WTFs:
+     * - Where is I2C_MSG_10BIT_ADDR handled?
+     */
     i2c_msg *msg = dev->msg;
 
     uint8 read = msg->flags & I2C_MSG_READ;
@@ -214,7 +375,7 @@ static void i2c_irq_handler(i2c_dev *dev) {
             /*
              * This should be impossible...
              */
-            throb();
+            ASSERT(0);
         }
         sr1 = sr2 = 0;
     }
@@ -288,20 +449,11 @@ static void i2c_irq_handler(i2c_dev *dev) {
     }
 }
 
-void __irq_i2c1_ev(void) {
-   i2c_irq_handler(&i2c_dev1);
-}
-
-void __irq_i2c2_ev(void) {
-   i2c_irq_handler(&i2c_dev2);
-}
-
-/**
- * @brief Interrupt handler for I2C error conditions
- * @param dev I2C device
- * @sideeffect Aborts any pending I2C transactions
+/*
+ * Interrupt handler for I2C error conditions. Aborts any pending I2C
+ * transactions.
  */
-static void i2c_irq_error_handler(i2c_dev *dev) {
+void _i2c_irq_error_handler(i2c_dev *dev) {
     I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
 
     dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR |
@@ -317,125 +469,34 @@ static void i2c_irq_error_handler(i2c_dev *dev) {
     dev->state = I2C_STATE_ERROR;
 }
 
-void __irq_i2c1_er(void) {
-    i2c_irq_error_handler(&i2c_dev1);
-}
-
-void __irq_i2c2_er(void) {
-    i2c_irq_error_handler(&i2c_dev2);
-}
-
-/**
- * @brief Reset an I2C bus.
- *
- * Reset is accomplished by clocking out pulses until any hung slaves
- * release SDA and SCL, then generating a START condition, then a STOP
- * condition.
- *
- * @param dev I2C device
- */
-void i2c_bus_reset(const i2c_dev *dev) {
-    /* Release both lines */
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD);
-
-    /*
-     * Make sure the bus is free by clocking it until any slaves release the
-     * bus.
-     */
-    while (!gpio_read_bit(dev->gpio_port, dev->sda_pin)) {
-        /* Wait for any clock stretching to finish */
-        while (!gpio_read_bit(dev->gpio_port, dev->scl_pin))
-            ;
-        delay_us(10);
-
-        /* Pull low */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
-        delay_us(10);
-
-        /* Release high again */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-        delay_us(10);
-    }
-
-    /* Generate start then stop condition */
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 0);
-    delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
-    delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-    delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
-}
-
-/**
- * @brief Initialize an I2C device and reset its registers to their
- *        default values.
- * @param dev Device to initialize.
+/*
+ * CCR/TRISE configuration helper
  */
-void i2c_init(i2c_dev *dev) {
-    rcc_reset_dev(dev->clk_id);
-    rcc_clk_enable(dev->clk_id);
-}
+static void set_ccr_trise(i2c_dev *dev, uint32 flags) {
+    uint32 ccr     = 0;
+    uint32 trise   = 0;
+    uint32 clk_mhz = _i2c_bus_clk(dev);
+    uint32 clk_hz  = clk_mhz * (1000 * 1000);
 
-/**
- * @brief Initialize an I2C device as bus master
- * @param dev Device to enable
- * @param flags Bitwise or of the following I2C options:
- *              I2C_FAST_MODE: 400 khz operation,
- *              I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
- *                             fast mode),
- *              I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
- *                             initialization,
- *              I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
- *              I2C_REMAP: Remap I2C1 to SCL/PB8 SDA/PB9.
- */
-void i2c_master_enable(i2c_dev *dev, uint32 flags) {
-#define I2C_CLK                (STM32_PCLK1/1000000)
-    uint32 ccr   = 0;
-    uint32 trise = 0;
-
-    /* PE must be disabled to configure the device */
-    ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
-
-    if ((dev == I2C1) && (flags & I2C_REMAP)) {
-        afio_remap(AFIO_REMAP_I2C1);
-        I2C1->sda_pin = 9;
-        I2C1->scl_pin = 8;
-    }
-
-    /* Reset the bus. Clock out any hung slaves. */
-    if (flags & I2C_BUS_RESET) {
-        i2c_bus_reset(dev);
-    }
-
-    /* Turn on clock and set GPIO modes */
-    i2c_init(dev);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
-
-    /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
-    i2c_set_input_clk(dev, I2C_CLK);
+    i2c_set_input_clk(dev, clk_mhz);
 
     if (flags & I2C_FAST_MODE) {
         ccr |= I2C_CCR_FS;
 
         if (flags & I2C_DUTY_16_9) {
             /* Tlow/Thigh = 16/9 */
-            ccr |= I2C_CCR_DUTY;
-            ccr |= STM32_PCLK1/(400000 * 25);
+            ccr |= I2C_CCR_DUTY_16_9;
+            ccr |= clk_hz / (400000 * 25);
         } else {
             /* Tlow/Thigh = 2 */
-            ccr |= STM32_PCLK1/(400000 * 3);
+            ccr |= clk_hz / (400000 * 3);
         }
 
-        trise = (300 * (I2C_CLK)/1000) + 1;
+        trise = (300 * clk_mhz / 1000) + 1;
     } else {
         /* Tlow/Thigh = 1 */
-        ccr = STM32_PCLK1/(100000 * 2);
-        trise = I2C_CLK + 1;
+        ccr = clk_hz / (100000 * 2);
+        trise = clk_mhz + 1;
     }
 
     /* Set minimum required value if CCR < 1*/
@@ -445,121 +506,4 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
 
     i2c_set_clk_control(dev, ccr);
     i2c_set_trise(dev, trise);
-
-    /* Enable event and buffer interrupts */
-    nvic_irq_enable(dev->ev_nvic_line);
-    nvic_irq_enable(dev->er_nvic_line);
-    i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
-
-    /*
-     * Important STM32 Errata:
-     *
-     * See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8),
-     * Section 2.11.1, 2.11.2.
-     *
-     * 2.11.1:
-     * When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not
-     * managed before the current byte is being transferred, problems may be
-     * encountered such as receiving an extra byte, reading the same data twice
-     * or missing data.
-     *
-     * 2.11.2:
-     * In Master Receiver mode, when closing the communication using
-     * method 2, the content of the last read data can be corrupted.
-     *
-     * If the user software is not able to read the data N-1 before the STOP
-     * condition is generated on the bus, the content of the shift register
-     * (data N) will be corrupted. (data N is shifted 1-bit to the left).
-     *
-     * ----------------------------------------------------------------------
-     *
-     * In order to ensure that events are not missed, the i2c interrupt must
-     * not be preempted. We set the i2c interrupt priority to be the highest
-     * interrupt in the system (priority level 0). All other interrupts have
-     * been initialized to priority level 16. See nvic_init().
-     */
-    nvic_irq_set_priority(dev->ev_nvic_line, 0);
-    nvic_irq_set_priority(dev->er_nvic_line, 0);
-
-    /* Make it go! */
-    i2c_peripheral_enable(dev);
-
-    dev->state = I2C_STATE_IDLE;
-}
-
-
-/**
- * @brief Process an i2c transaction.
- *
- * Transactions are composed of one or more i2c_msg's, and may be read
- * or write tranfers.  Multiple i2c_msg's will generate a repeated
- * start in between messages.
- *
- * @param dev I2C device
- * @param msgs Messages to send/receive
- * @param num Number of messages to send/receive
- * @param timeout Bus idle timeout in milliseconds before aborting the
- *                transfer.  0 denotes no timeout.
- * @return 0 on success,
- *         I2C_ERROR_PROTOCOL if there was a protocol error,
- *         I2C_ERROR_TIMEOUT if the transfer timed out.
- */
-int32 i2c_master_xfer(i2c_dev *dev,
-                      i2c_msg *msgs,
-                      uint16 num,
-                      uint32 timeout) {
-    int32 rc;
-
-    ASSERT(dev->state == I2C_STATE_IDLE);
-
-    dev->msg = msgs;
-    dev->msgs_left = num;
-    dev->timestamp = systick_uptime();
-    dev->state = I2C_STATE_BUSY;
-
-    i2c_enable_irq(dev, I2C_IRQ_EVENT);
-    i2c_start_condition(dev);
-
-    rc = wait_for_state_change(dev, I2C_STATE_XFER_DONE, timeout);
-    if (rc < 0) {
-        goto out;
-    }
-
-    dev->state = I2C_STATE_IDLE;
-out:
-    return rc;
-}
-
-
-/**
- * @brief Wait for an I2C event, or time out in case of error.
- * @param dev I2C device
- * @param state I2C_state state to wait for
- * @param timeout Timeout, in milliseconds
- * @return 0 if target state is reached, a negative value on error.
- */
-static inline int32 wait_for_state_change(i2c_dev *dev,
-                                          i2c_state state,
-                                          uint32 timeout) {
-    i2c_state tmp;
-
-    while (1) {
-        tmp = dev->state;
-
-        if (tmp == I2C_STATE_ERROR) {
-            return I2C_STATE_ERROR;
-        }
-
-        if (tmp == state) {
-            return 0;
-        }
-
-        if (timeout) {
-            if (systick_uptime() > (dev->timestamp + timeout)) {
-                /* TODO: overflow? */
-                /* TODO: racy? */
-                return I2C_ERROR_TIMEOUT;
-            }
-        }
-    }
 }

libmaple/i2c_private.h

@@ -0,0 +1,79 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifndef _LIBMAPLE_I2C_PRIVATE_H_
+#define _LIBMAPLE_I2C_PRIVATE_H_
+
+#include <libmaple/i2c_common.h>
+
+/* For old-style definitions (SDA/SCL on same GPIO device) */
+#define I2C_DEV_OLD(num, port, sda, scl)          \
+    {                                             \
+        .regs         = I2C##num##_BASE,          \
+        .gpio_port    = port,                     \
+        .scl_port     = NULL,                     \
+        .sda_port     = NULL,                     \
+        .sda_pin      = sda,                      \
+        .scl_pin      = scl,                      \
+        .clk_id       = RCC_I2C##num,             \
+        .ev_nvic_line = NVIC_I2C##num##_EV,       \
+        .er_nvic_line = NVIC_I2C##num##_ER,       \
+        .state        = I2C_STATE_DISABLED,       \
+    }
+
+/* For new-style definitions (SDA/SCL may be on different GPIO devices) */
+#define I2C_DEV_NEW(num, sdaport, sdabit, sclport, sclbit)          \
+    {                                                               \
+        .regs         = I2C##num##_BASE,                            \
+        .gpio_port    = NULL,                                       \
+        .scl_port     = sclport,                                    \
+        .scl_pin      = sclbit,                                     \
+        .sda_port     = sdaport,                                    \
+        .sda_pin      = sdabit,                                     \
+        .clk_id       = RCC_I2C##num,                               \
+        .ev_nvic_line = NVIC_I2C##num##_EV,                         \
+        .er_nvic_line = NVIC_I2C##num##_ER,                         \
+        .state        = I2C_STATE_DISABLED,                         \
+    }
+
+void _i2c_irq_handler(i2c_dev *dev);
+void _i2c_irq_error_handler(i2c_dev *dev);
+
+struct gpio_dev;
+
+static inline struct gpio_dev* scl_port(const i2c_dev *dev) {
+    return (dev->gpio_port == NULL) ? dev->scl_port : dev->gpio_port;
+}
+
+static inline struct gpio_dev* sda_port(const i2c_dev *dev) {
+    return (dev->gpio_port == NULL) ? dev->sda_port : dev->gpio_port;
+}
+
+/* Auxiliary procedure for enabling an I2C peripheral; `flags' as for
+ * i2c_master_enable(). */
+void _i2c_set_ccr_trise(i2c_dev *dev, uint32 flags);
+
+#endif  /* _LIBMAPLE_I2C_PRIVATE_H_ */

libmaple/adc.h → libmaple/include/libmaple/adc.h

@@ -1,6 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
+ * Copyright (c) 2012 LeafLabs, LLC.
  * Copyright (c) 2010 Perry Hung.
  *
  * Permission is hereby granted, free of charge, to any person
@@ -25,22 +26,29 @@
  *****************************************************************************/
 
 /**
- *  @file adc.h
- *
- *  @brief Analog-to-Digital Conversion (ADC) header.
+ * @file libmaple/include/libmaple/adc.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>,
+ *         Perry Hung <perry@leaflabs.com>
+ * @brief Analog-to-Digital Conversion (ADC) header.
  */
 
-#ifndef _ADC_H_
-#define _ADC_H_
-
-#include "libmaple.h"
-#include "bitband.h"
-#include "rcc.h"
+#ifndef _LIBMAPLE_ADC_H_
+#define _LIBMAPLE_ADC_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple.h>
+#include <libmaple/bitband.h>
+#include <libmaple/rcc.h>
+/* We include the series header below, after defining the register map
+ * and device structs. */
+
+/*
+ * Register map
+ */
+
 /** ADC register map type. */
 typedef struct adc_reg_map {
     __io uint32 SR;             ///< Status register
@@ -71,24 +79,30 @@ typedef struct adc_dev {
     rcc_clk_id clk_id; /**< RCC clock information */
 } adc_dev;
 
-extern const adc_dev *ADC1;
-extern const adc_dev *ADC2;
-#ifdef STM32_HIGH_DENSITY
-extern const adc_dev *ADC3;
-#endif
-
-/*
- * Register map base pointers
+/* Pull in the series header (which may need the above struct
+ * definitions).
+ *
+ * IMPORTANT: The series header must define the following:
+ *
+ * - enum adc_extsel_event (and typedef to adc_extsel_event): One per
+ *   external event used to trigger start of conversion of a regular
+ *   group. If two different series support the same event as a
+ *   trigger, they must use the same token for the enumerator for that
+ *   event. (The value of the enumerator is of course allowed to be
+ *   different).
+ *
+ * - enum adc_smp_rate (and typedef to adc_smp_rate): One per
+ *   available sampling time.  These must be in the form ADC_SMPR_X_Y
+ *   for X.Y cycles (e.g. ADC_SMPR_1_5 means 1.5 cycles), or
+ *   ADC_SMPR_X for X cycles (e.g. ADC_SMPR_3 means 3 cycles).
+ *
+ * - enum adc_prescaler (and typedef): One per available prescaler,
+ *   suitable for adc_set_prescaler. Series which have the same
+ *   prescaler dividers (e.g. STM32F1 and STM32F2 both divide PCLK2 by
+ *   2, 4, 6, or 8) must provide the same tokens as enumerators, for
+ *   portability.
  */
-
-/** ADC1 register map base pointer. */
-#define ADC1_BASE                       ((struct adc_reg_map*)0x40012400)
-/** ADC2 register map base pointer. */
-#define ADC2_BASE                       ((struct adc_reg_map*)0x40012800)
-#ifdef STM32_HIGH_DENSITY
-/** ADC3 register map base pointer. */
-#define ADC3_BASE                       ((struct adc_reg_map*)0x40013C00)
-#endif
+#include <series/adc.h>
 
 /*
  * Register bit definitions
@@ -136,31 +150,9 @@ extern const adc_dev *ADC3;
 
 /* Control register 2 */
 
-#define ADC_CR2_ADON_BIT                0
-#define ADC_CR2_CONT_BIT                1
-#define ADC_CR2_CAL_BIT                 2
-#define ADC_CR2_RSTCAL_BIT              3
-#define ADC_CR2_DMA_BIT                 8
-#define ADC_CR2_ALIGN_BIT               11
-#define ADC_CR2_JEXTTRIG_BIT            15
-#define ADC_CR2_EXTTRIG_BIT             20
-#define ADC_CR2_JSWSTART_BIT            21
-#define ADC_CR2_SWSTART_BIT             22
-#define ADC_CR2_TSEREFE_BIT             23
-
-#define ADC_CR2_ADON                    BIT(ADC_CR2_ADON_BIT)
-#define ADC_CR2_CONT                    BIT(ADC_CR2_CONT_BIT)
-#define ADC_CR2_CAL                     BIT(ADC_CR2_CAL_BIT)
-#define ADC_CR2_RSTCAL                  BIT(ADC_CR2_RSTCAL_BIT)
-#define ADC_CR2_DMA                     BIT(ADC_CR2_DMA_BIT)
-#define ADC_CR2_ALIGN                   BIT(ADC_CR2_ALIGN_BIT)
-#define ADC_CR2_JEXTSEL                 (0x7000)
-#define ADC_CR2_JEXTTRIG                BIT(ADC_CR2_JEXTTRIG_BIT)
-#define ADC_CR2_EXTSEL                  (0xE0000)
-#define ADC_CR2_EXTTRIG                 BIT(ADC_CR2_EXTTRIG_BIT)
-#define ADC_CR2_JSWSTART                BIT(ADC_CR2_JSWSTART_BIT)
-#define ADC_CR2_SWSTART                 BIT(ADC_CR2_SWSTART_BIT)
-#define ADC_CR2_TSEREFE                 BIT(ADC_CR2_TSEREFE_BIT)
+/* Because this register varies significantly by series (e.g. some
+ * bits moved and others disappeared in the F1->F2 transition), its
+ * definitions are in the series headers. */
 
 /* Sample time register 1 */
 
@@ -245,68 +237,51 @@ extern const adc_dev *ADC3;
 #define ADC_DR_ADC2DATA                 (0xFFFF << 16)
 #define ADC_DR_DATA                     0xFFFF
 
+/*
+ * Routines
+ */
+
 void adc_init(const adc_dev *dev);
+void adc_set_extsel(const adc_dev *dev, adc_extsel_event event);
+void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate);
+uint16 adc_read(const adc_dev *dev, uint8 channel);
 
 /**
- * @brief External event selector for regular group conversion.
- * @see adc_set_extsel
+ * @brief Set the ADC prescaler.
+ *
+ * This determines the ADC clock for all devices.
  */
-typedef enum adc_extsel_event {
-    ADC_ADC12_TIM1_CC1  = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */
-    ADC_ADC12_TIM1_CC2  = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */
-    ADC_ADC12_TIM1_CC3  = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */
-    ADC_ADC12_TIM2_CC2  = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */
-    ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */
-    ADC_ADC12_TIM4_CC4  = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */
-    ADC_ADC12_EXTI11    = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */
-#ifdef STM32_HIGH_DENSITY
-    ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO
-                                        event (high density only) */
-#endif
-    ADC_ADC12_SWSTART   = (7 << 17), /**< ADC1 and ADC2: Software start */
-#ifdef STM32_HIGH_DENSITY
-    ADC_ADC3_TIM3_CC1   = (0 << 17), /**< ADC3: Timer 3 CC1 event
-                                        (high density only) */
-    ADC_ADC3_TIM2_CC3   = (1 << 17), /**< ADC3: Timer 2 CC3 event
-                                        (high density only) */
-    ADC_ADC3_TIM1_CC3   = (2 << 17), /**< ADC3: Timer 1 CC3 event
-                                        (high density only) */
-    ADC_ADC3_TIM8_CC1   = (3 << 17), /**< ADC3: Timer 8 CC1 event
-                                        (high density only) */
-    ADC_ADC3_TIM8_TRGO  = (4 << 17), /**< ADC3: Timer 8 TRGO event
-                                        (high density only) */
-    ADC_ADC3_TIM5_CC1   = (5 << 17), /**< ADC3: Timer 5 CC1 event
-                                        (high density only) */
-    ADC_ADC3_TIM5_CC3   = (6 << 17), /**< ADC3: Timer 5 CC3 event
-                                        (high density only) */
-    ADC_ADC3_SWSTART    = (7 << 17), /**< ADC3: Software start (high
-                                        density only) */
-#endif
-    ADC_SWSTART         = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */
-} adc_extsel_event;
+extern void adc_set_prescaler(adc_prescaler pre);
 
-void adc_set_extsel(const adc_dev *dev, adc_extsel_event event);
-void adc_foreach(void (*fn)(const adc_dev*));
+/**
+ * @brief Call a function on all ADC devices.
+ * @param fn Function to call on each ADC device.
+ */
+extern void adc_foreach(void (*fn)(const adc_dev*));
 
+struct gpio_dev;
 /**
- * @brief ADC sample times, in ADC clock cycles
- *
- * These control the amount of time spent sampling the input voltage.
+ * @brief Configure a GPIO pin for ADC conversion.
+ * @param dev ADC device to use for conversion (currently ignored on
+ *            all targets).
+ * @param gdev GPIO device to configure.
+ * @param bit Bit on gdev to configure for ADC conversion.
  */
-typedef enum {
-    ADC_SMPR_1_5,               /**< 1.5 ADC cycles */
-    ADC_SMPR_7_5,               /**< 7.5 ADC cycles */
-    ADC_SMPR_13_5,              /**< 13.5 ADC cycles */
-    ADC_SMPR_28_5,              /**< 28.5 ADC cycles */
-    ADC_SMPR_41_5,              /**< 41.5 ADC cycles */
-    ADC_SMPR_55_5,              /**< 55.5 ADC cycles */
-    ADC_SMPR_71_5,              /**< 71.5 ADC cycles */
-    ADC_SMPR_239_5              /**< 239.5 ADC cycles */
-} adc_smp_rate;
+extern void adc_config_gpio(const struct adc_dev *dev,
+                            struct gpio_dev *gdev,
+                            uint8 bit);
 
-void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate);
-void adc_calibrate(const adc_dev *dev);
-uint16 adc_read(const adc_dev *dev, uint8 channel);
+/**
+ * @brief Enable an ADC and configure it for single conversion mode.
+ *
+ * This function performs any initialization necessary to allow the
+ * ADC device to perform a single synchronous regular software
+ * triggered conversion, using adc_read().
+ *
+ * @param dev Device to enable.
+ * @see adc_read()
+ */
+extern void adc_enable_single_swstart(const adc_dev* dev);
 
 /**
  * @brief Set the regular channel sequence length.
@@ -325,16 +300,6 @@ static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) {
 }
 
 /**
- * @brief Set external trigger conversion mode event for regular channels
- * @param dev    ADC device
- * @param enable If 1, conversion on external events is enabled; if 0,
- *               disabled.
- */
-static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
-    *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable;
-}
-
-/**
  * @brief Enable an adc peripheral
  * @param dev ADC device to enable
  */

libmaple/bitband.h → libmaple/include/libmaple/bitband.h

@@ -25,15 +25,19 @@
  *****************************************************************************/
 
 /**
- * @file bitband.h
+ * @file libmaple/include/libmaple/bitband.h
  *
  * @brief Bit-banding utility functions
  */
 
-#include "libmaple_types.h"
+#ifndef _LIBMAPLE_BITBAND_H_
+#define _LIBMAPLE_BITBAND_H_
 
-#ifndef _BITBAND_H_
-#define _BITBAND_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libmaple/libmaple_types.h>
 
 #define BB_SRAM_REF      0x20000000
 #define BB_SRAM_BASE     0x22000000
@@ -47,7 +51,7 @@ static inline volatile uint32* __bb_addr(volatile void*,
 
 /**
  * @brief Obtain a pointer to the bit-band address corresponding to a
- * bit in a volatile SRAM address.
+ *        bit in a volatile SRAM address.
  * @param address Address in the bit-banded SRAM region
  * @param bit     Bit in address to bit-band
  */
@@ -79,7 +83,7 @@ static inline void bb_sram_set_bit(volatile void *address,
 
 /**
  * @brief Obtain a pointer to the bit-band address corresponding to a
- * bit in a peripheral address.
+ *        bit in a peripheral address.
  * @param address Address in the bit-banded peripheral region
  * @param bit     Bit in address to bit-band
  */
@@ -117,4 +121,8 @@ static inline volatile uint32* __bb_addr(volatile void *address,
                               bit * 4);
 }
 
-#endif  /* _BITBAND_H_ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/bkp.h → libmaple/include/libmaple/bkp.h

@@ -25,19 +25,19 @@
  *****************************************************************************/
 
 /**
- * @file bkp.h
- * @brief Backup register support.
+ * @file libmaple/include/libmaple/bkp.h
+ * @brief Backup register support (STM32F1 only).
  */
 
-#ifndef _BKP_H_
-#define _BKP_H_
-
-#include "libmaple.h"
+#ifndef _LIBMAPLE_BKP_H_
+#define _LIBMAPLE_BKP_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <libmaple/libmaple.h>
+
 #if defined(STM32_MEDIUM_DENSITY)
 #define BKP_NR_DATA_REGS 10
 #elif defined(STM32_HIGH_DENSITY)
@@ -60,7 +60,7 @@ typedef struct bkp_reg_map {
     __io uint32 RTCCR;          ///< RTC control register
     __io uint32 CR;             ///< Control register
     __io uint32 CSR;            ///< Control and status register
-#ifdef STM32_HIGH_DENSITY
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
     const uint32 RESERVED2;     ///< Reserved
     const uint32 RESERVED3;     ///< Reserved
     __io uint32 DR11;           ///< Data register 11

libmaple/include/libmaple/dac.h

@@ -0,0 +1,158 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/dac.h
+ * @brief Digital to analog converter support.
+ */
+
+/* See notes/dac.txt for more info */
+
+#ifndef _LIBMAPLE_DAC_H_
+#define _LIBMAPLE_DAC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <series/dac.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+#include <libmaple/stm32.h>
+
+/*
+ * Register map base and device pointers.
+ *
+ * The DACs are the same on all supported targets, so it's not worth
+ * repeating these in the series headers.
+ */
+
+#define DAC_BASE                ((struct dac_reg_map*)0x40007400)
+
+/** DAC device type. */
+typedef struct dac_dev {
+    dac_reg_map *regs; /**< Register map */
+} dac_dev;
+
+#if STM32_HAVE_DAC
+extern const dac_dev *DAC;
+#endif
+
+/*
+ * Register bit definitions
+ */
+
+/* Control register */
+
+/* Channel 1 control */
+#define DAC_CR_EN1                  (1U << 0)  /* Enable */
+#define DAC_CR_BOFF1                (1U << 1)  /* Output buffer disable */
+#define DAC_CR_TEN1                 (1U << 2)  /* Trigger enable */
+#define DAC_CR_TSEL1                (0x7 << 3) /* Trigger selection */
+#define DAC_CR_WAVE1                (0x3 << 6) /* Noise/triangle wave */
+#define DAC_CR_MAMP1                (0xF << 8) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN1               (1U << 12) /* DMA enable */
+/* Channel 2 control */
+#define DAC_CR_EN2                  (1U << 16)  /* Enable */
+#define DAC_CR_BOFF2                (1U << 17)  /* Output buffer disable */
+#define DAC_CR_TEN2                 (1U << 18)  /* Trigger enable */
+#define DAC_CR_TSEL2                (0x7 << 19) /* Trigger selection */
+#define DAC_CR_WAVE2                (0x3 << 22) /* Noise/triangle wave */
+#define DAC_CR_MAMP2                (0xF << 24) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN2               (1U << 28)  /* DMA enable */
+
+/* Software trigger register */
+
+#define DAC_SWTRIGR_SWTRIG1         (1U << 0) /* Channel 1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2         (1U << 1) /* Channel 2 software trigger */
+
+/* Channel 1 12-bit right-aligned data holding register */
+
+#define DAC_DHR12R1_DACC1DHR        0x00000FFF
+
+/* Channel 1 12-bit left-aligned data holding register */
+
+#define DAC_DHR12L1_DACC1DHR        0x0000FFF0
+
+/* Channel 1 8-bit left-aligned data holding register */
+
+#define DAC_DHR8R1_DACC1DHR         0x000000FF
+
+/* Channel 2 12-bit right-aligned data holding register */
+
+#define DAC_DHR12R2_DACC2DHR        0x00000FFF
+
+/* Channel 2 12-bit left-aligned data holding register */
+
+#define DAC_DHR12L2_DACC2DHR        0x0000FFF0
+
+/* Channel 2 8-bit left-aligned data holding register */
+
+#define DAC_DHR8R2_DACC2DHR         0x000000FF
+
+/* Dual DAC 12-bit right-aligned data holding register */
+
+#define DAC_DHR12RD_DACC1DHR        0x00000FFF
+#define DAC_DHR12RD_DACC2DHR        0x0FFF0000
+
+/* Dual DAC 12-bit left-aligned data holding register */
+
+#define DAC_DHR12LD_DACC1DHR        0x0000FFF0
+#define DAC_DHR12LD_DACC2DHR        0xFFF00000
+
+/* Dual DAC 8-bit left-aligned data holding register */
+
+#define DAC_DHR8RD_DACC1DHR         0x000000FF
+#define DAC_DHR8RD_DACC2DHR         0x0000FF00
+
+/* Channel 1 data output register */
+
+#define DAC_DOR1_DACC1DOR           0x00000FFF
+
+/* Channel 1 data output register */
+
+#define DAC_DOR2_DACC2DOR           0x00000FFF
+
+/*
+ * Routines
+ */
+
+/* We take the dev argument in these for future-proofing */
+
+#define DAC_CH1 0x1
+#define DAC_CH2 0x2
+void dac_init(const dac_dev *dev, uint32 flags);
+
+void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val);
+void dac_enable_channel(const dac_dev *dev, uint8 channel);
+void dac_disable_channel(const dac_dev *dev, uint8 channel);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif

libmaple/include/libmaple/delay.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/delay.h
+ * @brief Delay implementation
+ */
+
+#ifndef _LIBMAPLE_DELAY_H_
+#define _LIBMAPLE_DELAY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/stm32.h>
+
+/**
+ * @brief Delay the given number of microseconds.
+ *
+ * @param us Number of microseconds to delay.
+ */
+static inline void delay_us(uint32 us) {
+    us *= STM32_DELAY_US_MULT;
+
+    /* fudge for function call overhead  */
+    us--;
+    asm volatile("   mov r0, %[us]          \n\t"
+                 "1: subs r0, #1            \n\t"
+                 "   bhi 1b                 \n\t"
+                 :
+                 : [us] "r" (us)
+                 : "r0");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/include/libmaple/dma.h

@@ -0,0 +1,444 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Michael Hope.
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/dma.h
+ *
+ * @author Marti Bolivar <mbolivar@leaflabs.com>;
+ *         Original implementation by Michael Hope
+ *
+ * @brief Direct Memory Access peripheral support
+ */
+
+#ifndef _LIBMAPLE_DMA_H_
+#define _LIBMAPLE_DMA_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/* <series/dma.h> provides:
+ *
+ * - An opaque dma_tube type, and predefined rvalues for each tube
+ *   supported by the series.
+ *
+ *   A "DMA tube" is a series-specific (hopefully integer) datatype
+ *   that abstracts the conduit through which DMA-ed data flow.
+ *
+ *   Examples: On STM32F1, dma_tube is just an alias for dma_channel,
+ *   and the tube values are just DMA_CH1 (=1), DMA_CH2 (=2), etc.
+ *
+ *   Note that a dma_tube doesn't have to be an enum, and its values
+ *   don't have to be integral. They _do_ need to be cheap to pass as
+ *   arguments, though.
+ *
+ * - struct dma_tube_reg_map (and typedef to dma_tube_reg_map). DMA
+ *   register maps tend to be split into global registers and per-tube
+ *   registers. It's convenient to pass around pointers to a tube's
+ *   registers, since that makes it possible to configure or otherwise
+ *   mess with a tube without knowing which one you're dealing with.
+ *
+ * - Base pointers to the various dma_tube_reg_maps.
+ *
+ *   Examples: On STM32F1, these are DMAxCHy_BASE. You can access
+ *   registers like DMAxCHy_BASE->CPAR, etc.
+ *
+ * - enum dma_request_src (and typedef to dma_request_src). This
+ *   specifies the peripheral DMA request sources (e.g. USART TX DMA
+ *   requests, etc.).
+ *
+ * - enum dma_mode_flags (and typedef to dma_mode_flags). Used in
+ *   dma_tube_config. If two series both support the same mode flags,
+ *   they must use the same enumerator names for those flags (the
+ *   values of those enumerators are of course allowed to differ).
+ *
+ * - Normal stuff: dma_reg_map and base pointers, register bit
+ *   definitions, dma_dev pointer declarations, and any other
+ *   convenience functions useful for the series. */
+#include <series/dma.h>
+/* <libmaple/dma_common.h> buys us dma_dev and other necessities. */
+#include <libmaple/dma_common.h>
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Declarations/documentation for some of the series-provided types.
+ */
+
+/**
+ * @brief (Series-dependent) DMA request sources.
+ *
+ * These specify the various pieces of peripheral functionality which
+ * may make DMA requests.  Use them to set up a DMA transfer (see
+ * struct dma_tube_config, dma_tube_cfg()).
+ */
+enum dma_request_src;
+
+/**
+ * @brief (Series-dependent) DMA tube configuration flags.
+ * These specify miscellaneous bits of configuration for a DMA tube.
+ * @see struct dma_mode_config
+ */
+enum dma_cfg_flags;
+
+/**
+ * @brief (Series-dependent) DMA tube register map type.
+ * This allows you to access a tube's registers as a group.
+ * @see dma_tube_regs()
+ */
+struct dma_tube_reg_map;
+
+/*
+ * Convenience functions
+ */
+
+/* Initialization */
+
+void dma_init(dma_dev *dev);
+
+/* dma_tube configuration
+ *
+ * Use these types and functions to set up DMA transfers, handle
+ * interrupts, etc. The main function of interest is dma_tube_cfg(),
+ * which the various series implement separately. */
+
+/**
+ * @brief Specifies a DMA tube configuration.
+ *
+ * Use one of these to set up a DMA transfer by passing it to
+ * dma_tube_cfg().
+ *
+ * @see dma_tube_cfg()
+ * @see dma_xfer_size
+ */
+typedef struct dma_tube_config {
+    /** Source of data */
+    __io void     *tube_src;
+    /** Source transfer size */
+    dma_xfer_size  tube_src_size;
+
+    /** Destination of data */
+    __io void     *tube_dst;
+    /** Destination transfer size */
+    dma_xfer_size  tube_dst_size;
+
+    /**
+     * Number of data to transfer (0 to 65,535).
+     *
+     * Note that this is NOT measured in bytes; it's measured in
+     * number of data, which occur in multiples of tube_src_size. For
+     * example, if tube_src_size is DMA_SIZE_32BITS and tube_nr_xfers
+     * is 2, then 8 total bytes will be transferred.
+     */
+    unsigned tube_nr_xfers;
+
+    /**
+     * Target-specific configuration flags.
+     *
+     * These are an OR of series-specific enum dma_mode_flags values.
+     * Consult the documentation for your target for what flags you
+     * can use here.
+     *
+     * Typical flag examples: DMA_CFG_SRC_INC, DMA_CFG_DST_INC,
+     * DMA_CFG_CIRC, DMA_CFG_CMPLT_IE, etc.
+     */
+    unsigned tube_flags;
+
+    /**
+     * Currently unused. You must set this to 0 or something valid for
+     * your target. */
+    void *target_data;
+
+    /**
+     * Hardware DMA request source.
+     *
+     * This is ignored for memory-to-memory transfers.
+     */
+    enum dma_request_src tube_req_src;
+} dma_tube_config;
+
+#define DMA_TUBE_CFG_SUCCESS 0
+#define DMA_TUBE_CFG_EREQ    1
+#define DMA_TUBE_CFG_ENDATA  2
+#define DMA_TUBE_CFG_EDEV    3
+#define DMA_TUBE_CFG_ESRC    4
+#define DMA_TUBE_CFG_EDST    5
+#define DMA_TUBE_CFG_EDIR    6
+#define DMA_TUBE_CFG_ESIZE   7
+#define DMA_TUBE_CFG_ECFG    0xFF
+/**
+ * @brief Configure a DMA tube.
+ *
+ * Use this function to set up a DMA transfer. The tube will be
+ * disabled before being reconfigured. The transfer will have low
+ * priority by default. You can choose another priority before the
+ * transfer begins using dma_set_priority(). You can manage your
+ * interrupt handlers for the tube using dma_attach_interrupt() and
+ * dma_detach_interrupt().
+ *
+ * After calling dma_tube_cfg() and performing any other desired
+ * configuration, start the transfer using dma_enable().
+ *
+ * @param dev  DMA device.
+ * @param tube DMA tube to configure.
+ * @param cfg  Configuration to apply to tube.
+ *
+ * @return DMA_TUBE_CFG_SUCCESS (0) on success, <0 on failure. On
+ *         failure, returned value will be the opposite (-) of one of:
+ *
+ *         - DMA_TUBE_CFG_EREQ: tube doesn't work with cfg->tube_req_src
+ *         - DMA_TUBE_CFG_ENDATA: cfg->tube_[src,dst]_size are
+ *           incompatible with cfg->tube_nr_xfers, or cfg->tube_nr_xfers
+ *           is out of bounds.
+ *         - DMA_TUBE_CFG_EDEV: dev does not support cfg
+ *         - DMA_TUBE_CFG_ESRC: bad cfg->tube_src
+ *         - DMA_TUBE_CFG_EDST: bad cfg->tube_dst
+ *         - DMA_TUBE_CFG_EDIR: dev can't transfer from cfg->tube_src to
+ *           cfg->tube_dst
+ *         - DMA_TUBE_CFG_ESIZE: something ended up wrong due to MSIZE/PSIZE
+ *         - DMA_TUBE_CFG_ECFG: generic "something's wrong"
+ *
+ * @sideeffect Disables tube. May alter tube's registers even when an
+ *             error occurs.
+ * @see struct dma_tube_config
+ * @see dma_attach_interrupt()
+ * @see dma_detach_interrupt()
+ * @see dma_enable()
+ */
+extern int dma_tube_cfg(dma_dev *dev, dma_tube tube, dma_tube_config *cfg);
+
+/* Other tube configuration functions. You can use these if
+ * dma_tube_cfg() isn't enough, or to adjust parts of an existing tube
+ * configuration. */
+
+/** DMA transfer priority. */
+typedef enum dma_priority {
+    DMA_PRIORITY_LOW       = 0, /**< Low priority */
+    DMA_PRIORITY_MEDIUM    = 1, /**< Medium priority */
+    DMA_PRIORITY_HIGH      = 2, /**< High priority */
+    DMA_PRIORITY_VERY_HIGH = 3, /**< Very high priority */
+} dma_priority;
+
+/**
+ * @brief Set the priority of a DMA transfer.
+ *
+ * You may not call this function while the tube is enabled.
+ *
+ * @param dev DMA device
+ * @param tube DMA tube
+ * @param priority priority to set.
+ */
+extern void dma_set_priority(dma_dev *dev, dma_tube tube,
+                             dma_priority priority);
+
+/**
+ * @brief Set the number of data transfers on a DMA tube.
+ *
+ * You may not call this function while the tube is enabled.
+ *
+ * @param dev DMA device
+ * @param tube Tube through which the transfer will occur.
+ * @param num_transfers Number of DMA transactions to set.
+ */
+extern void dma_set_num_transfers(dma_dev *dev, dma_tube tube,
+                                  uint16 num_transfers);
+
+/**
+ * @brief Set the base memory address where data will be read from or
+ *        written to.
+ *
+ * You must not call this function while the tube is enabled.
+ *
+ * If the DMA memory size is 16 bits, the address is automatically
+ * aligned to a half-word.  If the DMA memory size is 32 bits, the
+ * address is aligned to a word.
+ *
+ * @param dev DMA Device
+ * @param tube Tube whose base memory address to set.
+ * @param address Memory base address to use.
+ */
+extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address);
+
+/**
+ * @brief Set the base peripheral address where data will be read from
+ *        or written to.
+ *
+ * You must not call this function while the channel is enabled.
+ *
+ * If the DMA peripheral size is 16 bits, the address is automatically
+ * aligned to a half-word. If the DMA peripheral size is 32 bits, the
+ * address is aligned to a word.
+ *
+ * @param dev DMA Device
+ * @param tube Tube whose peripheral data register base address to set.
+ * @param addr Peripheral memory base address to use.
+ */
+extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __io void *address);
+
+/* Interrupt handling */
+
+/**
+ * @brief Attach an interrupt to a DMA transfer.
+ *
+ * Interrupts are enabled using series-specific mode flags in
+ * dma_tube_cfg().
+ *
+ * @param dev DMA device
+ * @param tube Tube to attach handler to
+ * @param handler Interrupt handler to call when tube interrupt fires.
+ * @see dma_tube_cfg()
+ * @see dma_get_irq_cause()
+ * @see dma_detach_interrupt()
+ */
+extern void dma_attach_interrupt(dma_dev *dev, dma_tube tube,
+                                 void (*handler)(void));
+
+
+/**
+ * @brief Detach a DMA transfer interrupt handler.
+ *
+ * After calling this function, the given tube's interrupts will be
+ * disabled.
+ *
+ * @param dev DMA device
+ * @param tube Tube whose handler to detach
+ * @sideeffect Clears the tube's interrupt enable bits.
+ * @see dma_attach_interrupt()
+ */
+extern void dma_detach_interrupt(dma_dev *dev, dma_tube tube);
+
+/* Tube enable/disable */
+
+/**
+ * @brief Enable a DMA tube.
+ *
+ * If the tube has been properly configured, calling this function
+ * allows it to start serving DMA requests.
+ *
+ * @param dev DMA device
+ * @param tube Tube to enable
+ * @see dma_tube_cfg()
+ */
+extern void dma_enable(dma_dev *dev, dma_tube tube);
+
+/**
+ * @brief Disable a DMA channel.
+ *
+ * Calling this function makes the tube stop serving DMA requests.
+ *
+ * @param dev DMA device
+ * @param tube Tube to disable
+ */
+extern void dma_disable(dma_dev *dev, dma_tube tube);
+
+/**
+ * @brief Check if a DMA tube is enabled.
+ * @param dev DMA device.
+ * @param tube Tube to check.
+ * @return 0 if the tube is disabled, >0 if it is enabled.
+ */
+static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube);
+
+/* Other conveniences */
+
+/**
+ * @brief Obtain a pointer to an individual DMA tube's registers.
+ *
+ * Examples:
+ *
+ * - On STM32F1, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1.
+ *
+ * @param dev DMA device.
+ * @param tube DMA tube whose register map to obtain.
+ * @return (Series-specific) tube register map.
+ */
+static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube);
+
+/**
+ * Encodes the reason why a DMA interrupt was called.
+ * @see dma_get_irq_cause()
+ */
+typedef enum dma_irq_cause {
+    DMA_TRANSFER_COMPLETE,      /**< Transfer is complete. */
+    DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */
+    DMA_TRANSFER_ERROR,         /**< Error occurred during transfer. */
+    DMA_TRANSFER_DME_ERROR,     /**<
+                                 * @brief Direct mode error occurred during
+                                 *        transfer. */
+    DMA_TRANSFER_FIFO_ERROR,    /**< FIFO error occurred during transfer. */
+} dma_irq_cause;
+
+/**
+ * @brief Discover the reason why a DMA interrupt was called.
+ *
+ * You may only call this function within an attached interrupt
+ * handler for the given channel.
+ *
+ * This function resets the internal DMA register state which encodes
+ * the cause of the interrupt; consequently, it can only be called
+ * once per interrupt handler invocation.
+ *
+ * @param dev DMA device
+ * @param tube Tube whose interrupt is being handled.
+ * @return Reason why the interrupt fired.
+ * @sideeffect Clears flags in dev's interrupt status registers.
+ * @see dma_attach_interrupt()
+ * @see dma_irq_cause
+ */
+extern dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_tube tube);
+
+/**
+ * @brief Get the ISR status bits for a DMA channel.
+ *
+ * The bits are returned right-aligned, in the order they appear in
+ * the corresponding ISR register.
+ *
+ * If you're trying to figure out why a DMA interrupt fired, you may
+ * find dma_get_irq_cause() more convenient.
+ *
+ * @param dev DMA device
+ * @param tube Tube whose ISR bits to return.
+ * @see dma_get_irq_cause().
+ */
+static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube);
+
+/**
+ * @brief Clear the ISR status bits for a given DMA tube.
+ *
+ * If you're trying to clean up after yourself in a DMA interrupt, you
+ * may find dma_get_irq_cause() more convenient.
+ *
+ * @param dev DMA device
+ * @param tube Tube whose ISR bits to clear.
+ * @see dma_get_irq_cause()
+ */
+static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif

libmaple/include/libmaple/dma_common.h

@@ -0,0 +1,114 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/dma_common.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief Common DMA sub-header for <series/dma.h> and <libmaple/dma.h>.
+ *
+ * WARNING: CONTENTS UNSTABLE
+ *
+ * The existence of this file is an implementation detail.  Its
+ * contents are not stable, so never include it directly.  If you need
+ * something from here, #include <libmaple/dma.h> instead.
+ */
+
+/*
+ * There's a fair amount of common DMA functionality needed by each
+ * <series/dma.h> and <libmaple/dma.h>.  This header exists in order
+ * to provide it to both, avoiding some hacks and circular
+ * dependencies.
+ */
+
+#ifndef _LIBMAPLE_DMA_COMMON_H_
+#define _LIBMAPLE_DMA_COMMON_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+#include <libmaple/rcc.h>
+
+/*
+ * Devices
+ */
+
+struct dma_reg_map;
+
+/* Encapsulates state related to user interrupt handlers. You
+ * shouldn't touch these directly; use dma_attach_interrupt() and
+ * dma_detach_interupt() instead. */
+typedef struct dma_handler_config {
+    void (*handler)(void);     /* User handler */
+    nvic_irq_num irq_line;     /* IRQ line for interrupt */
+} dma_handler_config;
+
+/** DMA device type */
+typedef struct dma_dev {
+    struct dma_reg_map        *regs;       /**< Register map */
+    rcc_clk_id                 clk_id;     /**< Clock ID */
+    struct dma_handler_config  handlers[]; /**< For internal use */
+} dma_dev;
+
+/**
+ * @brief DMA channels
+ *
+ * Notes:
+ * - This is also the dma_tube type for STM32F1.
+ * - Channel 0 is not available on all STM32 series.
+ *
+ * @see dma_tube
+ */
+typedef enum dma_channel {
+    DMA_CH0 = 0,                /**< Channel 0 */
+    DMA_CH1 = 1,                /**< Channel 1 */
+    DMA_CH2 = 2,                /**< Channel 2 */
+    DMA_CH3 = 3,                /**< Channel 3 */
+    DMA_CH4 = 4,                /**< Channel 4 */
+    DMA_CH5 = 5,                /**< Channel 5 */
+    DMA_CH6 = 6,                /**< Channel 6 */
+    DMA_CH7 = 7,                /**< Channel 7 */
+} dma_channel;
+
+/**
+ * @brief Source and destination transfer sizes.
+ * Use these when initializing a struct dma_tube_config.
+ * @see struct dma_tube_config
+ * @see dma_tube_cfg
+ */
+typedef enum dma_xfer_size {
+    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = 2,        /**< 32-bit transfers */
+} dma_xfer_size;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif

libmaple/exti.h → libmaple/include/libmaple/exti.h

@@ -25,22 +25,26 @@
  *****************************************************************************/
 
 /**
- * @file exti.h
- * @brief External interrupt control prototypes and defines
+ * @file libmaple/include/libmaple/exti.h
+ * @brief External interrupt control
  */
 
 /* See notes/exti.txt for more info */
 
-#include "libmaple.h"
-#include "gpio.h"
-
-#ifndef _EXTI_H_
-#define _EXTI_H_
+#ifndef _LIBMAPLE_EXTI_H_
+#define _LIBMAPLE_EXTI_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <series/exti.h>        /* provides EXTI_BASE */
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Register map and base pointer.
+ */
+
 /** EXTI register map type */
 typedef struct exti_reg_map {
     __io uint32 IMR;   /**< Interrupt mask register */
@@ -51,8 +55,50 @@ typedef struct exti_reg_map {
     __io uint32 PR;    /**< Pending register */
 } exti_reg_map;
 
-/** EXTI register map base pointer */
-#define EXTI_BASE                       ((struct exti_reg_map*)0x40010400)
+/*
+ * Types: exti_num, exti_cfg, exti_trigger_mode.
+ *
+ * A combination of these three specifies an external interrupt
+ * configuration (see exti_attach_interrupt()).
+ */
+
+/** EXTI line. */
+typedef enum exti_num {
+    EXTI0,    /**< EXTI line 0 */
+    EXTI1,    /**< EXTI line 1 */
+    EXTI2,    /**< EXTI line 2 */
+    EXTI3,    /**< EXTI line 3 */
+    EXTI4,    /**< EXTI line 4 */
+    EXTI5,    /**< EXTI line 5 */
+    EXTI6,    /**< EXTI line 6 */
+    EXTI7,    /**< EXTI line 7 */
+    EXTI8,    /**< EXTI line 8 */
+    EXTI9,    /**< EXTI line 9 */
+    EXTI10,   /**< EXTI line 10 */
+    EXTI11,   /**< EXTI line 11 */
+    EXTI12,   /**< EXTI line 12 */
+    EXTI13,   /**< EXTI line 13 */
+    EXTI14,   /**< EXTI line 14 */
+    EXTI15,   /**< EXTI line 15 */
+} exti_num;
+
+/**
+ * @brief EXTI port configuration
+ *
+ * These specify which GPIO port an external interrupt line should be
+ * connected to.
+ */
+typedef enum exti_cfg {
+    EXTI_PA,                    /**< Use PAx pin */
+    EXTI_PB,                    /**< Use PBx pin */
+    EXTI_PC,                    /**< Use PCx pin */
+    EXTI_PD,                    /**< Use PDx pin */
+    EXTI_PE,                    /**< Use PEx pin */
+    EXTI_PF,                    /**< Use PFx pin */
+    EXTI_PG,                    /**< Use PGx pin */
+    EXTI_PH,                    /**< Use PHx pin */
+    EXTI_PI,                    /**< Use PIx pin */
+} exti_cfg;
 
 /** External interrupt trigger mode */
 typedef enum exti_trigger_mode {
@@ -61,11 +107,29 @@ typedef enum exti_trigger_mode {
     EXTI_RISING_FALLING  /**< Trigger on both the rising and falling edges */
 } exti_trigger_mode;
 
-void exti_attach_interrupt(afio_exti_num num,
-                           afio_exti_port port,
+/*
+ * Routines
+ */
+
+void exti_attach_interrupt(exti_num num,
+                           exti_cfg port,
                            voidFuncPtr handler,
                            exti_trigger_mode mode);
-void exti_detach_interrupt(afio_exti_num num);
+void exti_detach_interrupt(exti_num num);
+
+/**
+ * @brief Set the GPIO port for an EXTI line.
+ *
+ * This is a low-level routine that most users will not
+ * need. exti_attach_interrupt() handles calling this function
+ * appropriately.
+ *
+ * @param num EXTI line
+ * @param port EXTI configuration for GPIO port to connect to num.
+ * @see exti_num
+ * @see exti_cfg
+ */
+extern void exti_select(exti_num num, exti_cfg port);
 
 #ifdef __cplusplus
 } // extern "C"

libmaple/include/libmaple/flash.h

@@ -0,0 +1,106 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/flash.h
+ * @brief Flash support.
+ */
+
+#ifndef _LIBMAPLE_FLASH_H_
+#define _LIBMAPLE_FLASH_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+#define FLASH_WAIT_STATE_0              0x0
+#define FLASH_WAIT_STATE_1              0x1
+#define FLASH_WAIT_STATE_2              0x2
+#define FLASH_WAIT_STATE_3              0x3
+#define FLASH_WAIT_STATE_4              0x4
+#define FLASH_WAIT_STATE_5              0x5
+#define FLASH_WAIT_STATE_6              0x6
+#define FLASH_WAIT_STATE_7              0x7
+
+/* The series header must define:
+ *
+ * - FLASH_SAFE_WAIT_STATES, the smallest number of wait states that
+ *   it is safe to use when SYSCLK is at its fastest documented rate
+ *   and the MCU is powered at 3.3V (i.e. this doesn't consider
+ *   overclocking or low voltage operation).
+ *
+ * - The following bit flags, for flash_enable_features():
+ *
+ *       -- FLASH_PREFETCH: prefetcher
+ *       -- FLASH_ICACHE: instruction cache
+ *       -- FLASH_DCACHE: data cache
+ *
+ *   See that function's Doxygen for more restrictions.
+ */
+#include <series/flash.h>
+
+#ifdef __DOXYGEN__
+/** Flash register map base pointer. */
+#define FLASH_BASE
+#endif
+
+/*
+ * Flash routines
+ */
+
+void flash_set_latency(uint32 wait_states);
+
+/**
+ * @brief Enable Flash memory features
+ *
+ * If the target MCU doesn't provide a feature (e.g. instruction and
+ * data caches on the STM32F1), the flag will be ignored. This allows
+ * using these flags unconditionally, with the desired effect taking
+ * place on targets that support them.
+ *
+ * @param feature_flags Bitwise OR of the following:
+ *                      FLASH_PREFETCH (turns on prefetcher),
+ *                      FLASH_ICACHE (turns on instruction cache),
+ *                      FLASH_DCACHE (turns on data cache).
+ */
+static inline void flash_enable_features(uint32 feature_flags) {
+    FLASH_BASE->ACR |= feature_flags;
+}
+
+/**
+ * @brief Deprecated. Use flash_enable_features(FLASH_PREFETCH) instead.
+ */
+static inline void flash_enable_prefetch(void) {
+    flash_enable_features(FLASH_PREFETCH);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/fsmc.h → libmaple/include/libmaple/fsmc.h

@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file fsmc.h
+ * @file libmaple/include/libmaple/fsmc.h
  * @brief Flexible static memory controller support.
  */
 
@@ -33,20 +33,19 @@
  * See ../notes/fsmc.txt for more info
  */
 
-#include "libmaple_types.h"
-
-/**
- * @file fsmc.h
- */
-
-#ifndef _FSMC_H_
-#define _FSMC_H_
+#ifndef _LIBMAPLE_FSMC_H_
+#define _LIBMAPLE_FSMC_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
-#ifdef STM32_HIGH_DENSITY
+#include <libmaple/libmaple_types.h>
+#include <libmaple/stm32.h>
+
+#if !STM32_HAVE_FSMC
+#error "FSMC is unavailable on your MCU"
+#endif
 
 /*
  * Register maps and devices
@@ -136,16 +135,16 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_BCR_MUXEN_BIT              1
 #define FSMC_BCR_MBKEN_BIT              0
 
-#define FSMC_BCR_CBURSTRW               BIT(FSMC_BCR_CBURSTRW_BIT)
-#define FSMC_BCR_ASYNCWAIT              BIT(FSMC_BCR_ASYNCWAIT_BIT)
-#define FSMC_BCR_EXTMOD                 BIT(FSMC_BCR_EXTMOD_BIT)
-#define FSMC_BCR_WAITEN                 BIT(FSMC_BCR_WAITEN_BIT)
-#define FSMC_BCR_WREN                   BIT(FSMC_BCR_WREN_BIT)
-#define FSMC_BCR_WAITCFG                BIT(FSMC_BCR_WAITCFG_BIT)
-#define FSMC_BCR_WRAPMOD                BIT(FSMC_BCR_WRAPMOD_BIT)
-#define FSMC_BCR_WAITPOL                BIT(FSMC_BCR_WAITPOL_BIT)
-#define FSMC_BCR_BURSTEN                BIT(FSMC_BCR_BURSTEN_BIT)
-#define FSMC_BCR_FACCEN                 BIT(FSMC_BCR_FACCEN_BIT)
+#define FSMC_BCR_CBURSTRW               (1U << FSMC_BCR_CBURSTRW_BIT)
+#define FSMC_BCR_ASYNCWAIT              (1U << FSMC_BCR_ASYNCWAIT_BIT)
+#define FSMC_BCR_EXTMOD                 (1U << FSMC_BCR_EXTMOD_BIT)
+#define FSMC_BCR_WAITEN                 (1U << FSMC_BCR_WAITEN_BIT)
+#define FSMC_BCR_WREN                   (1U << FSMC_BCR_WREN_BIT)
+#define FSMC_BCR_WAITCFG                (1U << FSMC_BCR_WAITCFG_BIT)
+#define FSMC_BCR_WRAPMOD                (1U << FSMC_BCR_WRAPMOD_BIT)
+#define FSMC_BCR_WAITPOL                (1U << FSMC_BCR_WAITPOL_BIT)
+#define FSMC_BCR_BURSTEN                (1U << FSMC_BCR_BURSTEN_BIT)
+#define FSMC_BCR_FACCEN                 (1U << FSMC_BCR_FACCEN_BIT)
 #define FSMC_BCR_MWID                   (0x3 << 4)
 #define FSMC_BCR_MWID_8BITS             (0x0 << 4)
 #define FSMC_BCR_MWID_16BITS            (0x1 << 4)
@@ -153,8 +152,8 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_BCR_MTYP_SRAM              (0x0 << 2)
 #define FSMC_BCR_MTYP_PSRAM             (0x1 << 2)
 #define FSMC_BCR_MTYP_NOR_FLASH         (0x2 << 2)
-#define FSMC_BCR_MUXEN                  BIT(FSMC_BCR_MUXEN_BIT)
-#define FSMC_BCR_MBKEN                  BIT(FSMC_BCR_MBKEN_BIT)
+#define FSMC_BCR_MUXEN                  (1U << FSMC_BCR_MUXEN_BIT)
+#define FSMC_BCR_MBKEN                  (1U << FSMC_BCR_MBKEN_BIT)
 
 /* SRAM/NOR-Flash chip-select timing registers */
 
@@ -199,15 +198,15 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_PCR_ECCPS_8192B             (0x5 << 17)
 #define FSMC_PCR_TAR                     (0xF << 13)
 #define FSMC_PCR_TCLR                    (0xF << 9)
-#define FSMC_PCR_ECCEN                   BIT(FSMC_PCR_ECCEN_BIT)
+#define FSMC_PCR_ECCEN                   (1U << FSMC_PCR_ECCEN_BIT)
 #define FSMC_PCR_PWID                    (0x3 << 4)
 #define FSMC_PCR_PWID_8BITS              (0x0 << 4)
 #define FSMC_PCR_PWID_16BITS             (0x1 << 4)
-#define FSMC_PCR_PTYP                    BIT(FSMC_PCR_PTYP_BIT)
+#define FSMC_PCR_PTYP                    (1U << FSMC_PCR_PTYP_BIT)
 #define FSMC_PCR_PTYP_PC_CF_PCMCIA       (0x0 << FSMC_PCR_PTYP_BIT)
 #define FSMC_PCR_PTYP_NAND               (0x1 << FSMC_PCR_PTYP_BIT)
-#define FSMC_PCR_PBKEN                   BIT(FSMC_PCR_PBKEN_BIT)
-#define FSMC_PCR_PWAITEN                 BIT(FSMC_PCR_PWAITEN_BIT)
+#define FSMC_PCR_PBKEN                   (1U << FSMC_PCR_PBKEN_BIT)
+#define FSMC_PCR_PWAITEN                 (1U << FSMC_PCR_PWAITEN_BIT)
 
 /* FIFO status and interrupt registers */
 
@@ -219,13 +218,13 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_SR_ILS_BIT                  1
 #define FSMC_SR_IRS_BIT                  0
 
-#define FSMC_SR_FEMPT                    BIT(FSMC_SR_FEMPT_BIT)
-#define FSMC_SR_IFEN                     BIT(FSMC_SR_IFEN_BIT)
-#define FSMC_SR_ILEN                     BIT(FSMC_SR_ILEN_BIT)
-#define FSMC_SR_IREN                     BIT(FSMC_SR_IREN_BIT)
-#define FSMC_SR_IFS                      BIT(FSMC_SR_IFS_BIT)
-#define FSMC_SR_ILS                      BIT(FSMC_SR_ILS_BIT)
-#define FSMC_SR_IRS                      BIT(FSMC_SR_IRS_BIT)
+#define FSMC_SR_FEMPT                    (1U << FSMC_SR_FEMPT_BIT)
+#define FSMC_SR_IFEN                     (1U << FSMC_SR_IFEN_BIT)
+#define FSMC_SR_ILEN                     (1U << FSMC_SR_ILEN_BIT)
+#define FSMC_SR_IREN                     (1U << FSMC_SR_IREN_BIT)
+#define FSMC_SR_IFS                      (1U << FSMC_SR_IFS_BIT)
+#define FSMC_SR_ILS                      (1U << FSMC_SR_ILS_BIT)
+#define FSMC_SR_IRS                      (1U << FSMC_SR_IRS_BIT)
 
 /* Common memory space timing registers */
 
@@ -252,35 +251,58 @@ typedef struct fsmc_nor_psram_reg_map {
  * Memory bank boundary addresses
  */
 
-/** Pointer to base address of FSMC memory bank 1 (split into 4
- * regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip)  */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 1 (NOR/PSRAM).
+ *
+ * This bank is split into 4 regions. Each region supports interfacing
+ * with 1 NOR Flash, SRAM, or PSRAM chip. The base addresses of these
+ * regions are FSMC_NOR_PSRAM_REGIONx, for x = 1, 2, 3, 4.
+ */
 #define FSMC_BANK1                      ((void*)0x60000000)
 
-/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 1, region 1
+ *        (NOR/PSRAM).
+ */
 #define FSMC_NOR_PSRAM_REGION1          FSMC_BANK1
 
-/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 1, region 2
+ *        (NOR/PSRAM).
+ */
 #define FSMC_NOR_PSRAM_REGION2          ((void*)0x64000000)
 
-/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 1, region 3
+ *        (NOR/PSRAM).
+ */
 #define FSMC_NOR_PSRAM_REGION3          ((void*)0x68000000)
 
-/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 1, region 4
+ *        (NOR/PSRAM).
+ */
 #define FSMC_NOR_PSRAM_REGION4          ((void*)0x6C000000)
 
-/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */
+/** Void pointer to base address of FSMC memory bank 2 (NAND Flash). */
 #define FSMC_BANK2                      ((void*)0x70000000)
 
-/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */
+/** Void pointer to base address of FSMC memory bank 3 (NAND Flash). */
 #define FSMC_BANK3                      ((void*)0x80000000)
 
-/** Pointer to base address of FSMC memory bank 4 (for PC card devices */
+/**
+ * @brief Void pointer to base address of FSMC memory bank 4 (PC card
+ *        devices).
+ */
 #define FSMC_BANK4                      ((void*)0x90000000)
 
 /*
  * SRAM/NOR Flash routines
  */
 
+/**
+ * @brief Configure FSMC GPIOs for use with SRAM.
+ */
 void fsmc_sram_init_gpios(void);
 
 /**
@@ -311,8 +333,6 @@ static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs,
     regs->BTR |= addset & 0xF;
 }
 
-#endif /* STM32_HIGH_DENSITY */
-
 #ifdef __cplusplus
 } /* extern "C" */
 #endif

libmaple/include/libmaple/gpio.h

@@ -0,0 +1,121 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/gpio.h
+ * @brief General Purpose I/O (GPIO) interace.
+ */
+
+#ifndef _LIBMAPLE_GPIO_H_
+#define _LIBMAPLE_GPIO_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*
+ * Note: Series header must define:
+ * - enum gpio_pin_mode (TODO think harder about portability here)
+ */
+#include <series/gpio.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+#include <libmaple/exti.h>
+
+/*
+ * Device type
+ */
+
+/** GPIO device type */
+typedef struct gpio_dev {
+    gpio_reg_map *regs;         /**< Register map */
+    rcc_clk_id    clk_id;       /**< RCC clock information */
+    /**
+     * @brief (Deprecated) External interrupt port.
+     * Instead of dev->exti_port, use gpio_exti_port(dev).
+     */
+    exti_cfg      exti_port;
+} gpio_dev;
+
+/*
+ * Portable routines
+ */
+
+void gpio_init(gpio_dev *dev);
+void gpio_init_all(void);
+/* TODO flags argument version? */
+void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
+
+/**
+ * @brief Get a GPIO port's corresponding EXTI port configuration.
+ * @param dev GPIO port whose exti_cfg to return.
+ */
+static inline exti_cfg gpio_exti_port(gpio_dev *dev) {
+    return (exti_cfg)(EXTI_PA + (dev->clk_id - RCC_GPIOA));
+}
+
+/**
+ * Set or reset a GPIO pin.
+ *
+ * Pin must have previously been configured to output mode.
+ *
+ * @param dev GPIO device whose pin to set.
+ * @param pin Pin on to set or reset
+ * @param val If true, set the pin.  If false, reset the pin.
+ */
+static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
+    val = !val;          /* "set" bits are lower than "reset" bits  */
+    dev->regs->BSRR = (1U << pin) << (16 * val);
+}
+
+/**
+ * Determine whether or not a GPIO pin is set.
+ *
+ * Pin must have previously been configured to input mode.
+ *
+ * @param dev GPIO device whose pin to test.
+ * @param pin Pin on dev to test.
+ * @return True if the pin is set, false otherwise.
+ */
+static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
+    return dev->regs->IDR & (1U << pin);
+}
+
+/**
+ * Toggle a pin configured as output push-pull.
+ * @param dev GPIO device.
+ * @param pin Pin on dev to toggle.
+ */
+static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
+    dev->regs->ODR = dev->regs->ODR ^ (1U << pin);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/i2c.h → libmaple/include/libmaple/i2c.h

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,17 +26,51 @@
  *****************************************************************************/
 
 /**
- * @file i2c.h
+ * @file libmaple/include/libmaple/i2c.h
  * @brief Inter-Integrated Circuit (I2C) peripheral support
+ *
+ * Currently master-only. Usage notes:
+ *
+ * - Enable an I2C device with i2c_master_enable().
+ * - Initialize an array of struct i2c_msg to suit the bus
+ *   transactions (reads/writes) you wish to perform.
+ * - Call i2c_master_xfer() to do the work.
  */
 
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "gpio.h"
+#ifndef _LIBMAPLE_I2C_H_
+#define _LIBMAPLE_I2C_H_
 
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Series header must provide:
+ *
+ * - uint32 _i2c_bus_clk(i2c_dev*): Clock frequency of dev's bus, in
+ *   MHz. (This is for internal use only).
+ *
+ * - (optional) _I2C_HAVE_IRQ_FIXUP: Leave undefined, or define to 1.
+ *   This is for internal use only. It's a hack to work around a
+ *   silicon bug related to I2C IRQ pre-emption on some targets. If 1,
+ *   the series header must also declare and implement a routine with
+ *   this signature (it may also be provided as a macro):
+ *
+ *       void _i2c_irq_priority_fixup(i2c_dev*)
+ *
+ *   This will be called by i2c_enable_irq() before actually enabling
+ *   I2C interrupts.
+ *
+ * - Reg. map base pointers, device pointer declarations.
+ */
+
+#include <series/i2c.h>
+#include <libmaple/i2c_common.h>
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/gpio.h>
 
 /** I2C register map type */
 typedef struct i2c_reg_map {
@@ -50,136 +85,118 @@ typedef struct i2c_reg_map {
     __io uint32 TRISE;          /**< TRISE (rise time) register */
 } i2c_reg_map;
 
-/** I2C device states */
-typedef enum i2c_state {
-    I2C_STATE_DISABLED          = 0, /**< Disabled */
-    I2C_STATE_IDLE              = 1, /**< Idle */
-    I2C_STATE_XFER_DONE         = 2, /**< Done with transfer */
-    I2C_STATE_BUSY              = 3, /**< Busy */
-    I2C_STATE_ERROR             = -1 /**< Error occurred */
-} i2c_state;
-
 /**
  * @brief I2C message type
  */
 typedef struct i2c_msg {
     uint16 addr;                /**< Address */
+
 #define I2C_MSG_READ            0x1
 #define I2C_MSG_10BIT_ADDR      0x2
-    uint16 flags;               /**< Bitwise OR of I2C_MSG_READ and
-                                     I2C_MSG_10BIT_ADDR */
+    /**
+     * Bitwise OR of:
+     * - I2C_MSG_READ (write is default)
+     * - I2C_MSG_10BIT_ADDR (7-bit is default) */
+    uint16 flags;
+
     uint16 length;              /**< Message length */
     uint16 xferred;             /**< Messages transferred */
     uint8 *data;                /**< Data */
 } i2c_msg;
 
-/**
- * @brief I2C device type.
- */
-typedef struct i2c_dev {
-    i2c_reg_map *regs;          /**< Register map */
-    gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
-    uint8 sda_pin;              /**< SDA bit on gpio_port */
-    uint8 scl_pin;              /**< SCL bit on gpio_port */
-    rcc_clk_id clk_id;          /**< RCC clock information */
-    nvic_irq_num ev_nvic_line;  /**< Event IRQ number */
-    nvic_irq_num er_nvic_line;  /**< Error IRQ number */
-    volatile i2c_state state;   /**< Device state */
-    uint16 msgs_left;           /**< Messages left */
-    i2c_msg *msg;               /**< Messages */
-    volatile uint32 timestamp;  /**< For internal use */
-    uint32 error_flags;         /**< Error flags, set on I2C error condition */
-} i2c_dev;
-
-/*
- * Devices
- */
-
-extern i2c_dev* const I2C1;
-extern i2c_dev* const I2C2;
-
-/*
- * Register map base pointers
- */
-
-/** I2C1 register map base pointer */
-#define I2C1_BASE               ((struct i2c_reg_map*)0x40005400)
-/** I2C2 register map base pointer */
-#define I2C2_BASE               ((struct i2c_reg_map*)0x40005800)
-
 /*
  * Register bit definitions
  */
 
 /* Control register 1 */
 
-#define I2C_CR1_SWRST           BIT(15)       // Software reset
-#define I2C_CR1_ALERT           BIT(13)       // SMBus alert
-#define I2C_CR1_PEC             BIT(12)       // Packet error checking
-#define I2C_CR1_POS             BIT(11)       // Acknowledge/PEC position
-#define I2C_CR1_ACK             BIT(10)       // Acknowledge enable
-#define I2C_CR1_START           BIT(8)        // Start generation
-#define I2C_CR1_STOP            BIT(9)        // Stop generation
-#define I2C_CR1_PE              BIT(0)        // Peripheral Enable
+#define I2C_CR1_SWRST           (1U << 15)    // Software reset
+#define I2C_CR1_ALERT           (1U << 13)    // SMBus alert
+#define I2C_CR1_PEC             (1U << 12)    // Packet error checking
+#define I2C_CR1_POS             (1U << 11)    // Acknowledge/PEC position
+#define I2C_CR1_ACK             (1U << 10)    // Acknowledge enable
+#define I2C_CR1_STOP            (1U << 9)     // Stop generation
+#define I2C_CR1_START           (1U << 8)     // Start generation
+#define I2C_CR1_NOSTRETCH       (1U << 7)     // Clock stretching disable
+#define I2C_CR1_ENGC            (1U << 6)     // General call enable
+#define I2C_CR1_ENPEC           (1U << 5)     // PEC enable
+#define I2C_CR1_ENARP           (1U << 4)     // ARP enable
+#define I2C_CR1_SMBTYPE         (1U << 3)     // SMBus type
+#define I2C_CR1_SMBTYPE_DEVICE  (0U << 3)     //     SMBus type: device
+#define I2C_CR1_SMBTYPE_HOST    (1U << 3)     //     SMBus type: host
+#define I2C_CR1_SMBUS           (1U << 1)     // SMBus mode
+#define I2C_CR1_SMBUS_I2C       (0U << 1)     //     SMBus mode: I2C
+#define I2C_CR1_SMBUS_SMBUS     (1U << 1)     //     SMBus mode: SMBus
+#define I2C_CR1_PE              (1U << 0)     // Peripheral Enable
 
 /* Control register 2 */
 
-#define I2C_CR2_LAST            BIT(12)       // DMA last transfer
-#define I2C_CR2_DMAEN           BIT(11)       // DMA requests enable
-#define I2C_CR2_ITBUFEN         BIT(10)       // Buffer interrupt enable
-#define I2C_CR2_ITEVTEN         BIT(9)        // Event interupt enable
-#define I2C_CR2_ITERREN         BIT(8)        // Error interupt enable
-#define I2C_CR2_FREQ            0xFFF         // Peripheral input frequency
+#define I2C_CR2_LAST            (1U << 12)    // DMA last transfer
+#define I2C_CR2_DMAEN           (1U << 11)    // DMA requests enable
+#define I2C_CR2_ITBUFEN         (1U << 10)    // Buffer interrupt enable
+#define I2C_CR2_ITEVTEN         (1U << 9)     // Event interupt enable
+#define I2C_CR2_ITERREN         (1U << 8)     // Error interupt enable
+#define I2C_CR2_FREQ            0x3F          // Peripheral input frequency
 
-/* Clock control register */
+/* Own address register 1 */
 
-#define I2C_CCR_FS              BIT(15)       // Fast mode selection
-#define I2C_CCR_DUTY            BIT(14)       // 16/9 duty ratio
-#define I2C_CCR_CCR             0xFFF         // Clock control bits
+#define I2C_OAR1_ADDMODE        (1U << 15)    // Addressing mode
+#define I2C_OAR1_ADDMODE_7_BIT  (0U << 15)    //     Addressing mode: 7-bit
+#define I2C_OAR1_ADDMODE_10_BIT (1U << 15)    //     Addressing mode: 10-bit
+#define I2C_OAR1_ADD            0x3FF         // Interface address
+
+/* Own address register 2 */
+
+#define I2C_OAR2_ADD2           0xFE          // Interface address
+#define I2C_OAR2_ENDUAL         1U            // Dual addressing mode enable
 
 /* Status register 1 */
 
-#define I2C_SR1_SB              BIT(0)        // Start bit
-#define I2C_SR1_ADDR            BIT(1)        // Address sent/matched
-#define I2C_SR1_BTF             BIT(2)        // Byte transfer finished
-#define I2C_SR1_ADD10           BIT(3)        // 10-bit header sent
-#define I2C_SR1_STOPF           BIT(4)        // Stop detection
-#define I2C_SR1_RXNE            BIT(6)        // Data register not empty
-#define I2C_SR1_TXE             BIT(7)        // Data register empty
-#define I2C_SR1_BERR            BIT(8)        // Bus error
-#define I2C_SR1_ARLO            BIT(9)        // Arbitration lost
-#define I2C_SR1_AF              BIT(10)       // Acknowledge failure
-#define I2C_SR1_OVR             BIT(11)       // Overrun/underrun
-#define I2C_SR1_PECERR          BIT(12)       // PEC Error in reception
-#define I2C_SR1_TIMEOUT         BIT(14)       // Timeout or Tlow error
-#define I2C_SR1_SMBALERT        BIT(15)       // SMBus alert
+#define I2C_SR1_SMBALERT        (1U << 15)    // SMBus alert
+#define I2C_SR1_TIMEOUT         (1U << 14)    // Timeout or Tlow error
+#define I2C_SR1_PECERR          (1U << 12)    // PEC Error in reception
+#define I2C_SR1_OVR             (1U << 11)    // Overrun/underrun
+#define I2C_SR1_AF              (1U << 10)    // Acknowledge failure
+#define I2C_SR1_ARLO            (1U << 9)     // Arbitration lost
+#define I2C_SR1_BERR            (1U << 8)     // Bus error
+#define I2C_SR1_TXE             (1U << 7)     // Data register empty
+#define I2C_SR1_RXNE            (1U << 6)     // Data register not empty
+#define I2C_SR1_STOPF           (1U << 4)     // Stop detection
+#define I2C_SR1_ADD10           (1U << 3)     // 10-bit header sent
+#define I2C_SR1_BTF             (1U << 2)     // Byte transfer finished
+#define I2C_SR1_ADDR            (1U << 1)     // Address sent/matched
+#define I2C_SR1_SB              (1U << 0)     // Start bit
 
 /* Status register 2 */
 
-#define I2C_SR2_MSL             BIT(0)        // Master/slave
-#define I2C_SR2_BUSY            BIT(1)        // Bus busy
-#define I2C_SR2_TRA             BIT(2)        // Transmitter/receiver
-#define I2C_SR2_GENCALL         BIT(4)        // General call address
-#define I2C_SR2_SMBDEFAULT      BIT(5)        // SMBus device default address
-#define I2C_SR2_SMBHOST         BIT(6)        // SMBus host header
-#define I2C_SR2_DUALF           BIT(7)        // Dual flag
 #define I2C_SR2_PEC             0xFF00        // Packet error checking register
+#define I2C_SR2_DUALF           (1U << 7)     // Dual flag
+#define I2C_SR2_SMBHOST         (1U << 6)     // SMBus host header
+#define I2C_SR2_SMBDEFAULT      (1U << 5)     // SMBus device default address
+#define I2C_SR2_GENCALL         (1U << 4)     // General call address
+#define I2C_SR2_TRA             (1U << 2)     // Transmitter/receiver
+#define I2C_SR2_BUSY            (1U << 1)     // Bus busy
+#define I2C_SR2_MSL             (1U << 0)     // Master/slave
+
+/* Clock control register */
+
+#define I2C_CCR_FS              (1U << 15)    // Fast mode selection
+#define I2C_CCR_DUTY            (1U << 14)    // Fast mode duty cycle
+#define I2C_CCR_DUTY_2_1        (0U << 14)    //     Fast mode duty: 2/1
+#define I2C_CCR_DUTY_16_9       (1U << 14)    //     Fast mode duty: 16/9
+#define I2C_CCR_CCR             0xFFF         // Clock control bits
 
 /*
  * Convenience routines
  */
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void i2c_init(i2c_dev *dev);
+/* Main I2C API */
 
 /* I2C enable options */
-#define I2C_FAST_MODE           BIT(0)      // 400 khz
-#define I2C_DUTY_16_9           BIT(1)      // 16/9 duty ratio
-#define I2C_REMAP               BIT(2)      // Use alternate pin mapping
-#define I2C_BUS_RESET           BIT(3)      // Perform a bus reset
+#define I2C_FAST_MODE           0x1           // 400 khz
+#define I2C_DUTY_16_9           0x2           // 16/9 duty ratio
+/* Flag 0x4 is reserved; DO NOT USE. */
+#define I2C_BUS_RESET           0x8           // Perform a bus reset
 void i2c_master_enable(i2c_dev *dev, uint32 flags);
 
 #define I2C_ERROR_PROTOCOL      (-1)
@@ -201,67 +218,7 @@ static inline void i2c_disable(i2c_dev *dev) {
     dev->state = I2C_STATE_DISABLED;
 }
 
-/**
- * @brief Turn on an I2C peripheral
- * @param dev Device to enable
- */
-static inline void i2c_peripheral_enable(i2c_dev *dev) {
-    dev->regs->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief Turn off an I2C peripheral
- * @param dev Device to turn off
- */
-static inline void i2c_peripheral_disable(i2c_dev *dev) {
-    dev->regs->CR1 &= ~I2C_CR1_PE;
-}
-
-/**
- * @brief Fill transmit register
- * @param dev I2C device
- * @param byte Byte to write
- */
-static inline void i2c_write(i2c_dev *dev, uint8 byte) {
-    dev->regs->DR = byte;
-}
-
-/**
- * @brief Set input clock frequency, in MHz
- * @param dev I2C device
- * @param freq Frequency in megahertz (2-36)
- */
-static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) {
-    uint32 cr2 = dev->regs->CR2;
-    cr2 &= ~I2C_CR2_FREQ;
-    cr2 |= freq;
-    dev->regs->CR2 = freq;
-}
-
-/**
- * @brief Set I2C clock control register. See RM008
- * @param dev I2C device
- * @param val Value to use for clock control register (in
- *            Fast/Standard mode)
- */
-static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) {
-    uint32 ccr = dev->regs->CCR;
-    ccr &= ~I2C_CCR_CCR;
-    ccr |= val;
-    dev->regs->CCR = ccr;
-}
-
-
-/**
- * @brief Set SCL rise time
- * @param dev I2C device
- * @param trise Maximum rise time in fast/standard mode (see RM0008
- *              for relevant formula).
- */
-static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) {
-    dev->regs->TRISE = trise;
-}
-
+/* Start/stop conditions */
 
 /**
  * @brief Generate a start condition on the bus.
@@ -297,6 +254,17 @@ static inline void i2c_stop_condition(i2c_dev *dev) {
 
 }
 
+/* IRQ enable/disable */
+
+#ifndef _I2C_HAVE_IRQ_FIXUP
+/* The series header provides this if _I2C_HAVE_IRQ_FIXUP is defined,
+ * but we need it either way. */
+#define _i2c_irq_priority_fixup(dev) ((void)0)
+#endif
+
+#define I2C_IRQ_ERROR              I2C_CR2_ITERREN
+#define I2C_IRQ_EVENT              I2C_CR2_ITEVTEN
+#define I2C_IRQ_BUFFER             I2C_CR2_ITBUFEN
 /**
  * @brief Enable one or more I2C interrupts
  * @param dev I2C device
@@ -305,10 +273,8 @@ static inline void i2c_stop_condition(i2c_dev *dev) {
  *             I2C_IRQ_EVENT (event interrupt), and
  *             I2C_IRQ_BUFFER (buffer interrupt).
  */
-#define I2C_IRQ_ERROR              I2C_CR2_ITERREN
-#define I2C_IRQ_EVENT              I2C_CR2_ITEVTEN
-#define I2C_IRQ_BUFFER             I2C_CR2_ITBUFEN
 static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) {
+    _i2c_irq_priority_fixup(dev);
     dev->regs->CR2 |= irqs;
 }
 
@@ -324,6 +290,7 @@ static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) {
     dev->regs->CR2 &= ~irqs;
 }
 
+/* ACK/NACK */
 
 /**
  * @brief Enable I2C acknowledgment
@@ -341,6 +308,104 @@ static inline void i2c_disable_ack(i2c_dev *dev) {
     dev->regs->CR1 &= ~I2C_CR1_ACK;
 }
 
+/* GPIO control */
+
+/**
+ * @brief Configure device GPIOs.
+ *
+ * Configure GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
+ * dev->gpio_port for use with I2C device dev.
+ *
+ * @param dev I2C Device
+ * @see i2c_release_gpios()
+ */
+extern void i2c_config_gpios(const i2c_dev *dev);
+
+/**
+ * @brief Release GPIOs controlling an I2C bus
+ *
+ * Releases the I2C bus controlled by dev as master, and disconnects
+ * GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
+ * dev->gpio_port from I2C device dev.
+ *
+ * @param dev I2C device
+ * @see i2c_config_gpios()
+ */
+extern void i2c_master_release_bus(const i2c_dev *dev);
+
+/* Miscellaneous low-level routines */
+
+void i2c_init(i2c_dev *dev);
+
+/**
+ * @brief Turn on an I2C peripheral
+ * @param dev Device to enable
+ */
+static inline void i2c_peripheral_enable(i2c_dev *dev) {
+    dev->regs->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief Turn off an I2C peripheral
+ * @param dev Device to turn off
+ */
+static inline void i2c_peripheral_disable(i2c_dev *dev) {
+    dev->regs->CR1 &= ~I2C_CR1_PE;
+}
+
+/**
+ * @brief Fill transmit register
+ * @param dev I2C device
+ * @param byte Byte to write
+ */
+static inline void i2c_write(i2c_dev *dev, uint8 byte) {
+    dev->regs->DR = byte;
+}
+
+/**
+ * @brief Set input clock frequency, in MHz
+ * @param dev I2C device
+ * @param freq Frequency, in MHz. This must be at least 2, and at most
+ *             the APB frequency of dev's bus. (For example, if
+ *             rcc_dev_clk(dev) == RCC_APB1, freq must be at most
+ *             PCLK1, in MHz). There is an additional limit of 46 MHz.
+ */
+static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) {
+#define I2C_MAX_FREQ_MHZ 46
+    ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ);
+    uint32 cr2 = dev->regs->CR2;
+    cr2 &= ~I2C_CR2_FREQ;
+    cr2 |= freq;
+    dev->regs->CR2 = freq;
+#undef I2C_MAX_FREQ_MHZ
+}
+
+/**
+ * @brief Set I2C clock control register.
+ *
+ * See the chip reference manual for the details.
+ *
+ * @param dev I2C device
+ * @param val Value to use for clock control register (in
+ *            Fast/Standard mode)
+ */
+static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) {
+    uint32 ccr = dev->regs->CCR;
+    ccr &= ~I2C_CCR_CCR;
+    ccr |= val;
+    dev->regs->CCR = ccr;
+}
+
+/**
+ * @brief Set SCL rise time
+ * @param dev I2C device
+ * @param trise Maximum rise time in fast/standard mode (see chip
+ *              reference manual for the relevant formulas).
+ */
+static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) {
+    dev->regs->TRISE = trise;
+}
+
 #ifdef __cplusplus
 }
 #endif

libmaple/include/libmaple/i2c_common.h

@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung (from <libmaple/i2c.h>).
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/i2c_common.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief This file is an implementation detail
+ *
+ * WARNING: CONTENTS UNSTABLE
+ *
+ * The existence of this file is an implementation detail.  Its
+ * contents are not stable, so never include it directly.  If you need
+ * something from here, #include <libmaple/i2c.h> instead.
+ */
+
+#ifndef _LIBMAPLE_I2C_COMMON_H_
+#define _LIBMAPLE_I2C_COMMON_H_
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+#include <libmaple/rcc.h>
+
+struct gpio_dev;
+struct i2c_reg_map;
+struct i2c_msg;
+
+/** I2C device states */
+typedef enum i2c_state {
+    I2C_STATE_DISABLED          = 0, /**< Disabled */
+    I2C_STATE_IDLE              = 1, /**< Idle */
+    I2C_STATE_XFER_DONE         = 2, /**< Done with transfer */
+    I2C_STATE_BUSY              = 3, /**< Busy */
+    I2C_STATE_ERROR             = -1 /**< Error occurred */
+} i2c_state;
+
+/**
+ * @brief I2C device type.
+ */
+typedef struct i2c_dev {
+    struct i2c_reg_map *regs;   /**< Register map */
+    struct i2c_msg *msg;        /**< Messages */
+    uint32 error_flags;         /**< Error flags, set on I2C error condition */
+    volatile uint32 timestamp;  /**< For internal use */
+
+    /**
+     * @brief Deprecated. Use .scl_port or .sda_port instead.
+     * If non-null, this will be used as SDA, SCL pins' GPIO port. If
+     * null, then .sda_port will be used for SDA, and .sda_port for
+     * SDA. */
+    struct gpio_dev *gpio_port;
+
+    /**
+     * @brief SDA GPIO device (but see .gpio_port).
+     */
+    struct gpio_dev *sda_port;
+
+    /**
+     * @brief SCL GPIO device (but see .gpio_port).
+     */
+    struct gpio_dev *scl_port;
+
+    uint16 msgs_left;           /**< Messages left */
+    uint8 sda_pin;              /**< SDA bit on gpio_port */
+    uint8 scl_pin;              /**< SCL bit on gpio_port */
+    rcc_clk_id clk_id;          /**< RCC clock information */
+    nvic_irq_num ev_nvic_line;  /**< Event IRQ number */
+    nvic_irq_num er_nvic_line;  /**< Error IRQ number */
+    volatile i2c_state state;   /**< Device state */
+} i2c_dev;
+
+#endif

libmaple/iwdg.h → libmaple/include/libmaple/iwdg.h

@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file iwdg.h
+ * @file libmaple/include/libmaple/iwdg.h
  * @author Michael Hope, Marti Bolivar <mbolivar@leaflabs.com>
  * @brief Independent watchdog support.
  *
@@ -38,16 +38,15 @@
  * Once started, the independent watchdog cannot be turned off.
  */
 
-#ifndef _IWDG_H_
-#define _IWDG_H_
-
-#include "libmaple_types.h"
-#include "util.h"
+#ifndef _LIBMAPLE_IWDG_H_
+#define _LIBMAPLE_IWDG_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple_types.h>
+
 /*
  * Register map
  */
@@ -88,8 +87,8 @@ typedef struct iwdg_reg_map {
 #define IWDG_SR_RVU_BIT                 1
 #define IWDG_SR_PVU_BIT                 0
 
-#define IWDG_SR_RVU                     BIT(IWDG_SR_RVU_BIT)
-#define IWDG_SR_PVU                     BIT(IWDG_SR_PVU_BIT)
+#define IWDG_SR_RVU                     (1U << IWDG_SR_RVU_BIT)
+#define IWDG_SR_PVU                     (1U << IWDG_SR_PVU_BIT)
 
 /**
  * @brief Independent watchdog prescalers.

libmaple/libmaple.h → libmaple/include/libmaple/libmaple.h

@@ -25,17 +25,21 @@
  *****************************************************************************/
 
 /**
- *  @file libmaple.h
+ *  @file libmaple/include/libmaple/libmaple.h
  *  @brief General include file for libmaple
  */
 
-#ifndef _LIBMAPLE_H_
-#define _LIBMAPLE_H_
+#ifndef _LIBMAPLE_LIBMAPLE_H_
+#define _LIBMAPLE_LIBMAPLE_H_
 
-#include "libmaple_types.h"
-#include "stm32.h"
-#include "util.h"
-#include "delay.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/stm32.h>
+#include <libmaple/util.h>
+#include <libmaple/delay.h>
 
 /*
  * Where to put usercode, based on space reserved for bootloader.
@@ -46,5 +50,8 @@
 #define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
 
+#ifdef __cplusplus
+}
 #endif
 
+#endif

libmaple/libmaple_types.h → libmaple/include/libmaple/libmaple_types.h

@@ -25,13 +25,17 @@
  *****************************************************************************/
 
 /**
- *  @file libmaple_types.h
+ *  @file libmaple/include/libmaple/libmaple_types.h
  *
- *  @brief libmaple types
+ *  @brief libmaple's types, and operations on types.
  */
 
-#ifndef _LIBMAPLE_TYPES_H_
-#define _LIBMAPLE_TYPES_H_
+#ifndef _LIBMAPLE_LIBMAPLE_TYPES_H_
+#define _LIBMAPLE_LIBMAPLE_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 typedef unsigned char uint8;
 typedef unsigned short uint16;
@@ -48,10 +52,21 @@ typedef void (*voidFuncPtr)(void);
 #define __io volatile
 #define __attr_flash __attribute__((section (".USER_FLASH")))
 #define __packed __attribute__((__packed__))
+#define __deprecated __attribute__((__deprecated__))
+#define __weak __attribute__((weak))
+#define __always_inline inline __attribute__((always_inline))
+#define __unused __attribute__((unused))
 
 #ifndef NULL
 #define NULL 0
 #endif
 
+#ifndef offsetof
+#define offsetof(type, member) __builtin_offsetof(type, member)
 #endif
 
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/include/libmaple/nvic.h

@@ -0,0 +1,155 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/nvic.h
+ * @brief Nested vectored interrupt controller support.
+ *
+ * Basic usage:
+ *
+ * @code
+ *   // Initialise the interrupt controller and point to the vector
+ *   // table at the start of flash.
+ *   nvic_init(0x08000000, 0);
+ *   // Bind in a timer interrupt handler
+ *   timer_attach_interrupt(TIMER_CC1_INTERRUPT, handler);
+ *   // Optionally set the priority
+ *   nvic_irq_set_priority(NVIC_TIMER1_CC, 5);
+ *   // All done, enable all interrupts
+ *   nvic_globalirq_enable();
+ * @endcode
+ */
+
+#ifndef _LIBMAPLE_NVIC_H_
+#define _LIBMAPLE_NVIC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/util.h>
+
+/** NVIC register map type. */
+typedef struct nvic_reg_map {
+    __io uint32 ISER[8];      /**< Interrupt Set Enable Registers */
+    /** Reserved */
+    uint32 RESERVED0[24];
+
+    __io uint32 ICER[8];      /**< Interrupt Clear Enable Registers */
+    /** Reserved */
+    uint32 RESERVED1[24];
+
+    __io uint32 ISPR[8];      /**< Interrupt Set Pending Registers */
+    /** Reserved */
+    uint32 RESERVED2[24];
+
+    __io uint32 ICPR[8];      /**< Interrupt Clear Pending Registers */
+    /** Reserved */
+    uint32 RESERVED3[24];
+
+    __io uint32 IABR[8];      /**< Interrupt Active bit Registers */
+    /** Reserved */
+    uint32 RESERVED4[56];
+
+    __io uint8  IP[240];      /**< Interrupt Priority Registers */
+    /** Reserved */
+    uint32 RESERVED5[644];
+
+    __io uint32 STIR;         /**< Software Trigger Interrupt Registers */
+} nvic_reg_map;
+
+/** NVIC register map base pointer. */
+#define NVIC_BASE                       ((struct nvic_reg_map*)0xE000E100)
+
+/*
+ * Note: The series header must define enum nvic_irq_num, which gives
+ * descriptive names to the interrupts and exceptions from NMI (-14)
+ * to the largest interrupt available in the series, where the value
+ * for nonnegative enumerators corresponds to its position in the
+ * vector table.
+ *
+ * It also must define a static inline nvic_irq_disable_all(), which
+ * writes 0xFFFFFFFF to all ICE registers available in the series. (We
+ * place the include here to give the series header access to
+ * NVIC_BASE, in order to let it do so).
+ */
+#include <series/nvic.h>
+
+void nvic_init(uint32 address, uint32 offset);
+void nvic_set_vector_table(uint32 address, uint32 offset);
+void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority);
+void nvic_sys_reset();
+
+/**
+ * Enables interrupts and configurable fault handlers (clear PRIMASK).
+ */
+static inline void nvic_globalirq_enable() {
+    asm volatile("cpsie i");
+}
+
+/**
+ * Disable interrupts and configurable fault handlers (set PRIMASK).
+ */
+static inline void nvic_globalirq_disable() {
+    asm volatile("cpsid i");
+}
+
+/**
+ * @brief Enable interrupt irq_num
+ * @param irq_num Interrupt to enable
+ */
+static inline void nvic_irq_enable(nvic_irq_num irq_num) {
+    if (irq_num < 0) {
+        return;
+    }
+    NVIC_BASE->ISER[irq_num / 32] = BIT(irq_num % 32);
+}
+
+/**
+ * @brief Disable interrupt irq_num
+ * @param irq_num Interrupt to disable
+ */
+static inline void nvic_irq_disable(nvic_irq_num irq_num) {
+    if (irq_num < 0) {
+        return;
+    }
+    NVIC_BASE->ICER[irq_num / 32] = BIT(irq_num % 32);
+}
+
+/**
+ * @brief Quickly disable all interrupts.
+ *
+ * Calling this function is significantly faster than calling
+ * nvic_irq_disable() in a loop.
+ */
+static inline void nvic_irq_disable_all(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/pwr.h → libmaple/include/libmaple/pwr.h

@@ -25,16 +25,20 @@
  *****************************************************************************/
 
 /**
- * @file pwr.h
- * @brief Power control (PWR) defines.
+ * @file libmaple/include/libmaple/pwr.h
+ * @brief Power control (PWR).
  */
 
-#include "libmaple.h"
+#ifndef _LIBMAPLE_PWR_H_
+#define _LIBMAPLE_PWR_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <libmaple/libmaple.h>
+#include <series/pwr.h>
+
 /** Power interface register map. */
 typedef struct pwr_reg_map {
     __io uint32 CR;      /**< Control register */
@@ -51,28 +55,52 @@ typedef struct pwr_reg_map {
 /* Control register */
 
 /** Disable backup domain write protection bit */
-#define PWR_CR_DBP  8
+#define PWR_CR_DBP_BIT                  8
 /** Power voltage detector enable bit */
-#define PWR_CR_PVDE 4
+#define PWR_CR_PVDE_BIT                 4
 /** Clear standby flag bit */
-#define PWR_CR_CSBF 3
+#define PWR_CR_CSBF_BIT                 3
 /** Clear wakeup flag bit */
-#define PWR_CR_CWUF 2
+#define PWR_CR_CWUF_BIT                 2
 /** Power down deepsleep bit */
-#define PWR_CR_PDDS 1
+#define PWR_CR_PDDS_BIT                 1
 /** Low-power deepsleep bit */
-#define PWR_CR_LPDS 0
+#define PWR_CR_LPDS_BIT                 0
+
+/** Disable backup domain write protection */
+#define PWR_CR_DBP                      (1U << PWR_CR_DBP_BIT)
+/** Power voltage detector (PVD) level selection */
+#define PWR_CR_PLS                      (0x7 << 5)
+/** Power voltage detector enable */
+#define PWR_CR_PVDE                     (1U << PWR_CR_PVDE_BIT)
+/** Clear standby flag */
+#define PWR_CR_CSBF                     (1U << PWR_CR_CSBF_BIT)
+/** Clear wakeup flag */
+#define PWR_CR_CWUF                     (1U << PWR_CR_CWUF_BIT)
+/** Power down deepsleep */
+#define PWR_CR_PDDS                     (1U << PWR_CR_PDDS_BIT)
+/** Low-power deepsleep */
+#define PWR_CR_LPDS                     (1U << PWR_CR_LPDS_BIT)
 
 /* Control and status register */
 
 /** Enable wakeup pin bit */
-#define PWR_CSR_EWUP 8
+#define PWR_CSR_EWUP_BIT                 8
 /** PVD output bit */
-#define PWR_CSR_PVDO 2
+#define PWR_CSR_PVDO_BIT                 2
 /** Standby flag bit */
-#define PWR_CSR_SBF  1
+#define PWR_CSR_SBF_BIT                  1
 /** Wakeup flag bit */
-#define PWR_CSR_WUF  0
+#define PWR_CSR_WUF_BIT                  0
+
+/** Enable wakeup pin */
+#define PWR_CSR_EWUP                     (1U << PWR_CSR_EWUP_BIT)
+/** PVD output */
+#define PWR_CSR_PVDO                     (1U << PWR_CSR_PVDO_BIT)
+/** Standby flag */
+#define PWR_CSR_SBF                      (1U << PWR_CSR_SBF_BIT)
+/** Wakeup flag */
+#define PWR_CSR_WUF                      (1U << PWR_CSR_WUF_BIT)
 
 /*
  * Convenience functions
@@ -83,3 +111,5 @@ void pwr_init(void);
 #ifdef __cplusplus
 }
 #endif
+
+#endif

libmaple/include/libmaple/rcc.h

@@ -0,0 +1,175 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/rcc.h
+ * @brief Reset and Clock Control (RCC) interface.
+ */
+
+#ifndef _LIBMAPLE_RCC_H_
+#define _LIBMAPLE_RCC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+/* Put the SYSCLK sources before the series header is included, as it
+ * might need them. */
+/**
+ * @brief SYSCLK sources
+ * @see rcc_switch_sysclk()
+ */
+typedef enum rcc_sysclk_src {
+    RCC_CLKSRC_HSI = 0x0,
+    RCC_CLKSRC_HSE = 0x1,
+    RCC_CLKSRC_PLL = 0x2,
+} rcc_sysclk_src;
+
+#include <series/rcc.h>
+
+/* Note: Beyond the usual (registers, etc.), it's up to the series
+ * header to define the following types:
+ *
+ * - enum rcc_clk: Available system and secondary clock sources,
+ *   e.g. RCC_CLK_HSE, RCC_CLK_PLL, RCC_CLK_LSE.
+ *
+ *   Note that the inclusion of secondary clock sources (like LSI and
+ *   LSE) makes enum rcc_clk different from the SYSCLK sources, which
+ *   are defined in this header as enum rcc_sysclk_src.
+ *
+ *   IMPORTANT NOTE TO IMPLEMENTORS: If you are adding support for a
+ *   new STM32 series, see the comment near rcc_clk_reg() in
+ *   libmaple/rcc.c for information on how to choose these values so
+ *   that rcc_turn_on_clk() etc. will work on your series.
+ *
+ * - enum rcc_clk_id: For each available peripheral. These are widely used
+ *   as unique IDs (TODO extricate from RCC?). Peripherals which are
+ *   common across STM32 series should use the same token for their
+ *   rcc_clk_id in each series header.
+ *
+ * - enum rcc_clk_domain: For each clock domain. This is returned by
+ *   rcc_dev_clk(). For instance, each AHB and APB is a clock domain.
+ *
+ * - enum rcc_prescaler: And a suitable set of dividers for
+ *   rcc_set_prescaler().
+ *
+ * - enum rcc_pllsrc: For each PLL source. Same source, same token.
+ *
+ * - A target-dependent type to be pointed to by the data field in a
+ *   struct rcc_pll_cfg.
+ */
+
+#ifdef __DOXYGEN__
+/** RCC register map base pointer */
+#define RCC_BASE
+#endif
+
+/* Clock prescaler management. */
+
+/**
+ * @brief Set the divider on a peripheral prescaler
+ * @param prescaler prescaler to set
+ * @param divider prescaler divider
+ */
+extern void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
+
+/* SYSCLK. */
+
+void rcc_switch_sysclk(rcc_sysclk_src sysclk_src);
+
+/* PLL configuration */
+
+/**
+ * @brief Specifies a configuration for the main PLL.
+ */
+typedef struct rcc_pll_cfg {
+    rcc_pllsrc  pllsrc;     /**< PLL source */
+
+    /** Series-specific configuration data. */
+    void       *data;
+} rcc_pll_cfg;
+
+/**
+ * @brief Configure the main PLL.
+ *
+ * You may only call this function while the PLL is disabled.
+ *
+ * @param pll_cfg Desired PLL configuration. The contents of this
+ *                struct depend entirely on the target.
+ */
+extern void rcc_configure_pll(rcc_pll_cfg *pll_cfg);
+
+/* System and secondary clock sources. */
+
+void rcc_turn_on_clk(rcc_clk clock);
+void rcc_turn_off_clk(rcc_clk clock);
+int rcc_is_clk_on(rcc_clk clock);
+int rcc_is_clk_ready(rcc_clk clock);
+
+/* Peripheral clock lines and clock domains. */
+
+/**
+ * @brief Turn on the clock line on a peripheral
+ * @param id Clock ID of the peripheral to turn on.
+ */
+extern void rcc_clk_enable(rcc_clk_id id);
+
+/**
+ * @brief Reset a peripheral.
+ *
+ * Caution: not all rcc_clk_id values refer to a peripheral which can
+ * be reset. (Only rcc_clk_ids for peripherals with bits in an RCC
+ * reset register can be used here.)
+ *
+ * @param id Clock ID of the peripheral to reset.
+ */
+extern void rcc_reset_dev(rcc_clk_id id);
+
+rcc_clk_domain rcc_dev_clk(rcc_clk_id id);
+
+/* Clock security system */
+
+/**
+ * @brief Enable the clock security system (CSS).
+ */
+static inline void rcc_enable_css() {
+    RCC_BASE->CR |= RCC_CR_CSSON;
+}
+
+/**
+ * @brief Disable the clock security system (CSS).
+ */
+static inline void rcc_disable_css() {
+    RCC_BASE->CR &= ~RCC_CR_CSSON;
+}
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif

libmaple/ring_buffer.h → libmaple/include/libmaple/ring_buffer.h

@@ -25,22 +25,22 @@
  *****************************************************************************/
 
 /**
- * @file ring_buffer.h
+ * @file libmaple/include/libmaple/ring_buffer.h
  * @brief Simple circular buffer
  *
  * This implementation is not thread-safe.  In particular, none of
  * these functions is guaranteed re-entrant.
  */
 
-#ifndef _RING_BUFFER_H_
-#define _RING_BUFFER_H_
-
-#include "libmaple_types.h"
+#ifndef _LIBMAPLE_RING_BUFFER_H_
+#define _LIBMAPLE_RING_BUFFER_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple_types.h>
+
 /**
  * Ring buffer type.
  *
@@ -186,4 +186,3 @@ static inline void rb_reset(ring_buffer *rb) {
 #endif
 
 #endif
-

libmaple/scb.h → libmaple/include/libmaple/scb.h

@@ -25,14 +25,18 @@
  *****************************************************************************/
 
 /**
- * @file scb.h
+ * @file libmaple/include/libmaple/scb.h
  * @brief System control block header
  */
 
-#include "libmaple_types.h"
+#ifndef _LIBMAPLE_SCB_H_
+#define _LIBMAPLE_SCB_H_
 
-#ifndef _SCB_H_
-#define _SCB_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libmaple/libmaple_types.h>
 
 /*
  * Register map and base pointer
@@ -198,4 +202,8 @@ typedef struct scb_reg_map {
 #define SCB_DFSR_BKPT                   BIT(1)
 #define SCB_DFSR_HALTED                 BIT(0)
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif

libmaple/spi.h → libmaple/include/libmaple/spi.h

@@ -1,6 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  * Copyright (c) 2010 Perry Hung.
  *
  * Permission is hereby granted, free of charge, to any person
@@ -25,7 +26,7 @@
  *****************************************************************************/
 
 /**
- * @file spi.h
+ * @file libmaple/include/libmaple/spi.h
  * @author Marti Bolivar <mbolivar@leaflabs.com>
  * @brief Serial Peripheral Interface (SPI) and Integrated
  *        Interchip Sound (I2S) peripheral support.
@@ -33,19 +34,18 @@
  * I2S support is currently limited to register maps and bit definitions.
  */
 
-#ifndef _SPI_H_
-#define _SPI_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "gpio.h"
-#include "util.h"
+#ifndef _LIBMAPLE_SPI_H_
+#define _LIBMAPLE_SPI_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <series/spi.h>
+
 /*
  * Register maps
  */
@@ -63,13 +63,6 @@ typedef struct spi_reg_map {
     __io uint32 I2SPR;          /**< I2S prescaler register */
 } spi_reg_map;
 
-/** SPI1 register map base pointer */
-#define SPI1_BASE                       ((struct spi_reg_map*)0x40013000)
-/** SPI2 register map base pointer */
-#define SPI2_BASE                       ((struct spi_reg_map*)0x40003800)
-/** SPI3 register map base pointer */
-#define SPI3_BASE                       ((struct spi_reg_map*)0x40003C00)
-
 /*
  * Register bit definitions
  */
@@ -90,20 +83,20 @@ typedef struct spi_reg_map {
 #define SPI_CR1_CPOL_BIT                1
 #define SPI_CR1_CPHA_BIT                0
 
-#define SPI_CR1_BIDIMODE                BIT(SPI_CR1_BIDIMODE_BIT)
+#define SPI_CR1_BIDIMODE                (1U << SPI_CR1_BIDIMODE_BIT)
 #define SPI_CR1_BIDIMODE_2_LINE         (0x0 << SPI_CR1_BIDIMODE_BIT)
 #define SPI_CR1_BIDIMODE_1_LINE         (0x1 << SPI_CR1_BIDIMODE_BIT)
-#define SPI_CR1_BIDIOE                  BIT(SPI_CR1_BIDIOE_BIT)
-#define SPI_CR1_CRCEN                   BIT(SPI_CR1_CRCEN_BIT)
-#define SPI_CR1_CRCNEXT                 BIT(SPI_CR1_CRCNEXT_BIT)
-#define SPI_CR1_DFF                     BIT(SPI_CR1_DFF_BIT)
+#define SPI_CR1_BIDIOE                  (1U << SPI_CR1_BIDIOE_BIT)
+#define SPI_CR1_CRCEN                   (1U << SPI_CR1_CRCEN_BIT)
+#define SPI_CR1_CRCNEXT                 (1U << SPI_CR1_CRCNEXT_BIT)
+#define SPI_CR1_DFF                     (1U << SPI_CR1_DFF_BIT)
 #define SPI_CR1_DFF_8_BIT               (0x0 << SPI_CR1_DFF_BIT)
 #define SPI_CR1_DFF_16_BIT              (0x1 << SPI_CR1_DFF_BIT)
-#define SPI_CR1_RXONLY                  BIT(SPI_CR1_RXONLY_BIT)
-#define SPI_CR1_SSM                     BIT(SPI_CR1_SSM_BIT)
-#define SPI_CR1_SSI                     BIT(SPI_CR1_SSI_BIT)
-#define SPI_CR1_LSBFIRST                BIT(SPI_CR1_LSBFIRST_BIT)
-#define SPI_CR1_SPE                     BIT(SPI_CR1_SPE_BIT)
+#define SPI_CR1_RXONLY                  (1U << SPI_CR1_RXONLY_BIT)
+#define SPI_CR1_SSM                     (1U << SPI_CR1_SSM_BIT)
+#define SPI_CR1_SSI                     (1U << SPI_CR1_SSI_BIT)
+#define SPI_CR1_LSBFIRST                (1U << SPI_CR1_LSBFIRST_BIT)
+#define SPI_CR1_SPE                     (1U << SPI_CR1_SPE_BIT)
 #define SPI_CR1_BR                      (0x7 << 3)
 #define SPI_CR1_BR_PCLK_DIV_2           (0x0 << 3)
 #define SPI_CR1_BR_PCLK_DIV_4           (0x1 << 3)
@@ -113,17 +106,14 @@ typedef struct spi_reg_map {
 #define SPI_CR1_BR_PCLK_DIV_64          (0x5 << 3)
 #define SPI_CR1_BR_PCLK_DIV_128         (0x6 << 3)
 #define SPI_CR1_BR_PCLK_DIV_256         (0x7 << 3)
-#define SPI_CR1_MSTR                    BIT(SPI_CR1_MSTR_BIT)
-#define SPI_CR1_CPOL                    BIT(SPI_CR1_CPOL_BIT)
+#define SPI_CR1_MSTR                    (1U << SPI_CR1_MSTR_BIT)
+#define SPI_CR1_CPOL                    (1U << SPI_CR1_CPOL_BIT)
 #define SPI_CR1_CPOL_LOW                (0x0 << SPI_CR1_CPOL_BIT)
 #define SPI_CR1_CPOL_HIGH               (0x1 << SPI_CR1_CPOL_BIT)
-#define SPI_CR1_CPHA                    BIT(SPI_CR1_CPHA_BIT)
+#define SPI_CR1_CPHA                    (1U << SPI_CR1_CPHA_BIT)
 
 /* Control register 2 */
 
-/* RM0008-ism: SPI CR2 has "TXDMAEN" and "RXDMAEN" bits, while the
- * USARTs have CR3 "DMAR" and "DMAT" bits. */
-
 #define SPI_CR2_TXEIE_BIT               7
 #define SPI_CR2_RXNEIE_BIT              6
 #define SPI_CR2_ERRIE_BIT               5
@@ -131,12 +121,12 @@ typedef struct spi_reg_map {
 #define SPI_CR2_TXDMAEN_BIT             1
 #define SPI_CR2_RXDMAEN_BIT             0
 
-#define SPI_CR2_TXEIE                   BIT(SPI_CR2_TXEIE_BIT)
-#define SPI_CR2_RXNEIE                  BIT(SPI_CR2_RXNEIE_BIT)
-#define SPI_CR2_ERRIE                   BIT(SPI_CR2_ERRIE_BIT)
-#define SPI_CR2_SSOE                    BIT(SPI_CR2_SSOE_BIT)
-#define SPI_CR2_TXDMAEN                 BIT(SPI_CR2_TXDMAEN_BIT)
-#define SPI_CR2_RXDMAEN                 BIT(SPI_CR2_RXDMAEN_BIT)
+#define SPI_CR2_TXEIE                   (1U << SPI_CR2_TXEIE_BIT)
+#define SPI_CR2_RXNEIE                  (1U << SPI_CR2_RXNEIE_BIT)
+#define SPI_CR2_ERRIE                   (1U << SPI_CR2_ERRIE_BIT)
+#define SPI_CR2_SSOE                    (1U << SPI_CR2_SSOE_BIT)
+#define SPI_CR2_TXDMAEN                 (1U << SPI_CR2_TXDMAEN_BIT)
+#define SPI_CR2_RXDMAEN                 (1U << SPI_CR2_RXDMAEN_BIT)
 
 /* Status register */
 
@@ -149,37 +139,35 @@ typedef struct spi_reg_map {
 #define SPI_SR_TXE_BIT                  1
 #define SPI_SR_RXNE_BIT                 0
 
-#define SPI_SR_BSY                      BIT(SPI_SR_BSY_BIT)
-#define SPI_SR_OVR                      BIT(SPI_SR_OVR_BIT)
-#define SPI_SR_MODF                     BIT(SPI_SR_MODF_BIT)
-#define SPI_SR_CRCERR                   BIT(SPI_SR_CRCERR_BIT)
-#define SPI_SR_UDR                      BIT(SPI_SR_UDR_BIT)
-#define SPI_SR_CHSIDE                   BIT(SPI_SR_CHSIDE_BIT)
+#define SPI_SR_BSY                      (1U << SPI_SR_BSY_BIT)
+#define SPI_SR_OVR                      (1U << SPI_SR_OVR_BIT)
+#define SPI_SR_MODF                     (1U << SPI_SR_MODF_BIT)
+#define SPI_SR_CRCERR                   (1U << SPI_SR_CRCERR_BIT)
+#define SPI_SR_UDR                      (1U << SPI_SR_UDR_BIT)
+#define SPI_SR_CHSIDE                   (1U << SPI_SR_CHSIDE_BIT)
 #define SPI_SR_CHSIDE_LEFT              (0x0 << SPI_SR_CHSIDE_BIT)
 #define SPI_SR_CHSIDE_RIGHT             (0x1 << SPI_SR_CHSIDE_BIT)
-#define SPI_SR_TXE                      BIT(SPI_SR_TXE_BIT)
-#define SPI_SR_RXNE                     BIT(SPI_SR_RXNE_BIT)
+#define SPI_SR_TXE                      (1U << SPI_SR_TXE_BIT)
+#define SPI_SR_RXNE                     (1U << SPI_SR_RXNE_BIT)
 
 /* I2S configuration register */
 
-/* RM0008-ism: CR1 has "CPOL", I2SCFGR has "CKPOL". */
-
 #define SPI_I2SCFGR_I2SMOD_BIT          11
 #define SPI_I2SCFGR_I2SE_BIT            10
 #define SPI_I2SCFGR_PCMSYNC_BIT         7
 #define SPI_I2SCFGR_CKPOL_BIT           3
 #define SPI_I2SCFGR_CHLEN_BIT           0
 
-#define SPI_I2SCFGR_I2SMOD              BIT(SPI_I2SCFGR_I2SMOD_BIT)
+#define SPI_I2SCFGR_I2SMOD              (1U << SPI_I2SCFGR_I2SMOD_BIT)
 #define SPI_I2SCFGR_I2SMOD_SPI          (0x0 << SPI_I2SCFGR_I2SMOD_BIT)
 #define SPI_I2SCFGR_I2SMOD_I2S          (0x1 << SPI_I2SCFGR_I2SMOD_BIT)
-#define SPI_I2SCFGR_I2SE                BIT(SPI_I2SCFGR_I2SE_BIT)
+#define SPI_I2SCFGR_I2SE                (1U << SPI_I2SCFGR_I2SE_BIT)
 #define SPI_I2SCFGR_I2SCFG              (0x3 << 8)
 #define SPI_I2SCFGR_I2SCFG_SLAVE_TX     (0x0 << 8)
 #define SPI_I2SCFGR_I2SCFG_SLAVE_RX     (0x1 << 8)
 #define SPI_I2SCFGR_I2SCFG_MASTER_TX    (0x2 << 8)
 #define SPI_I2SCFGR_I2SCFG_MASTER_RX    (0x3 << 8)
-#define SPI_I2SCFGR_PCMSYNC             BIT(SPI_I2SCFGR_PCMSYNC_BIT)
+#define SPI_I2SCFGR_PCMSYNC             (1U << SPI_I2SCFGR_PCMSYNC_BIT)
 #define SPI_I2SCFGR_PCMSYNC_SHORT       (0x0 << SPI_I2SCFGR_PCMSYNC_BIT)
 #define SPI_I2SCFGR_PCMSYNC_LONG        (0x1 << SPI_I2SCFGR_PCMSYNC_BIT)
 #define SPI_I2SCFGR_I2SSTD              (0x3 << 4)
@@ -187,17 +175,26 @@ typedef struct spi_reg_map {
 #define SPI_I2SCFGR_I2SSTD_MSB          (0x1 << 4)
 #define SPI_I2SCFGR_I2SSTD_LSB          (0x2 << 4)
 #define SPI_I2SCFGR_I2SSTD_PCM          (0x3 << 4)
-#define SPI_I2SCFGR_CKPOL               BIT(SPI_I2SCFGR_CKPOL_BIT)
+#define SPI_I2SCFGR_CKPOL               (1U << SPI_I2SCFGR_CKPOL_BIT)
 #define SPI_I2SCFGR_CKPOL_LOW           (0x0 << SPI_I2SCFGR_CKPOL_BIT)
 #define SPI_I2SCFGR_CKPOL_HIGH          (0x1 << SPI_I2SCFGR_CKPOL_BIT)
 #define SPI_I2SCFGR_DATLEN              (0x3 << 1)
 #define SPI_I2SCFGR_DATLEN_16_BIT       (0x0 << 1)
 #define SPI_I2SCFGR_DATLEN_24_BIT       (0x1 << 1)
 #define SPI_I2SCFGR_DATLEN_32_BIT       (0x2 << 1)
-#define SPI_I2SCFGR_CHLEN               BIT(SPI_I2SCFGR_CHLEN_BIT)
+#define SPI_I2SCFGR_CHLEN               (1U << SPI_I2SCFGR_CHLEN_BIT)
 #define SPI_I2SCFGR_CHLEN_16_BIT        (0x0 << SPI_I2SCFGR_CHLEN_BIT)
 #define SPI_I2SCFGR_CHLEN_32_BIT        (0x1 << SPI_I2SCFGR_CHLEN_BIT)
 
+/* I2S prescaler register */
+
+#define SPI_I2SPR_MCKOE_BIT             9
+#define SPI_I2SPR_ODD_BIT               8
+
+#define SPI_I2SPR_MCKOE                 (1U << SPI_I2SPR_MCKOE_BIT)
+#define SPI_I2SPR_ODD                   (1U << SPI_I2SPR_ODD_BIT)
+#define SPI_I2SPR_I2SDIV                0xFF
+
 /*
  * Devices
  */
@@ -209,42 +206,54 @@ typedef struct spi_dev {
     nvic_irq_num irq_num;       /**< NVIC interrupt number */
 } spi_dev;
 
-extern spi_dev *SPI1;
-extern spi_dev *SPI2;
-#ifdef STM32_HIGH_DENSITY
-extern spi_dev *SPI3;
-#endif
-
 /*
  * SPI Convenience functions
  */
 
 void spi_init(spi_dev *dev);
 
-void spi_gpio_cfg(uint8 as_master,
-                  gpio_dev *nss_dev,
-                  uint8 nss_bit,
-                  gpio_dev *comm_dev,
-                  uint8 sck_bit,
-                  uint8 miso_bit,
-                  uint8 mosi_bit);
+struct gpio_dev;
+/**
+ * @brief Configure GPIO bit modes for use as a SPI port's pins.
+ * @param as_master If true, configure bits for use as a bus master.
+ *                  Otherwise, configure bits for use as slave.
+ * @param nss_dev NSS pin's GPIO device
+ * @param comm_dev SCK, MISO, MOSI pins' GPIO device
+ * @param nss_bit NSS pin's GPIO bit on nss_dev
+ * @param sck_bit SCK pin's GPIO bit on comm_dev
+ * @param miso_bit MISO pin's GPIO bit on comm_dev
+ * @param mosi_bit MOSI pin's GPIO bit on comm_dev
+ */
+extern void spi_config_gpios(spi_dev *dev,
+                             uint8 as_master,
+                             struct gpio_dev *nss_dev,
+                             uint8 nss_bit,
+                             struct gpio_dev *comm_dev,
+                             uint8 sck_bit,
+                             uint8 miso_bit,
+                             uint8 mosi_bit);
 
 /**
  * @brief SPI mode configuration.
  *
- * Determines a combination of clock polarity (CPOL), which determines
- * idle state of the clock line, and clock phase (CPHA), which
- * determines which clock edge triggers data capture.
+ * A SPI mode determines a combination of the idle state of the clock
+ * line (the clock polarity, or "CPOL"), and which clock edge triggers
+ * data capture (the clock phase, or "CPHA").
  */
 typedef enum spi_mode {
-    SPI_MODE_0,  /**< Clock line idles low (0), data capture on first
-                    clock transition. */
-    SPI_MODE_1,  /**< Clock line idles low (0), data capture on second
-                    clock transition */
-    SPI_MODE_2,  /**< Clock line idles high (1), data capture on first
-                    clock transition. */
-    SPI_MODE_3   /**< Clock line idles high (1), data capture on
-                    second clock transition. */
+    /** Clock idles low, data captured on rising edge (first transition) */
+    SPI_MODE_LOW_RISING = 0,
+    /** Clock idles low, data captured on falling edge (second transition) */
+    SPI_MODE_LOW_FALLING = 1,
+    /** Clock idles high, data captured on falling edge (first transition) */
+    SPI_MODE_HIGH_FALLING = 2,
+    /** Clock idles high, data captured on rising edge (second transition) */
+    SPI_MODE_HIGH_RISING = 3,
+
+    SPI_MODE_0 = SPI_MODE_LOW_RISING,   /**< Same as SPI_MODE_LOW_RISING */
+    SPI_MODE_1 = SPI_MODE_LOW_FALLING,  /**< Same as SPI_MODE_LOW_FALLING */
+    SPI_MODE_2 = SPI_MODE_HIGH_FALLING, /**< Same as SPI_MODE_HIGH_FALLING */
+    SPI_MODE_3 = SPI_MODE_HIGH_RISING,  /**< Same as SPI_MODE_HIGH_RISING */
 } spi_mode;
 
 /**
@@ -299,7 +308,11 @@ void spi_slave_enable(spi_dev *dev,
 
 uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len);
 
-void spi_foreach(void (*fn)(spi_dev (*dev)));
+/**
+ * @brief Call a function on each SPI port
+ * @param fn Function to call.
+ */
+extern void spi_foreach(void (*fn)(spi_dev*));
 
 void spi_peripheral_enable(spi_dev *dev);
 void spi_peripheral_disable(spi_dev *dev);

libmaple/include/libmaple/stm32.h

@@ -0,0 +1,237 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010, 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/stm32.h
+ * @brief STM32 chip header
+ *
+ * This header supplies various chip-specific values for the current
+ * build target. It's useful both to abstract away hardware details
+ * (e.g. through use of STM32_NR_INTERRUPTS) and to decide what to do
+ * when you want something nonportable (e.g. by checking
+ * STM32_MCU_SERIES).
+ */
+
+#ifndef _LIBMAPLE_STM32_H_
+#define _LIBMAPLE_STM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * STM32 series identifiers.
+ *
+ * Don't make these into an enum; the preprocessor needs them.
+ */
+
+/** STM32F1 series. */
+#define STM32_SERIES_F1 0
+/** STM32F2 series. */
+#define STM32_SERIES_F2 1
+/** STM32L1 series. */
+#define STM32_SERIES_L1 2
+/** STM32F4 series. */
+#define STM32_SERIES_F4 3
+
+/* The series header is responsible for defining:
+ *
+ * - Everything in the following __DOXYGEN__ conditional block.
+ *
+ * - STM32_HAVE_FSMC: 1 if the MCU has the FSMC peripheral, and 0
+ *   otherwise.
+ *
+ * - STM32_HAVE_USB: 1 if the MCU has a USB peripheral, and 0
+ *   otherwise.
+ */
+#include <series/stm32.h>
+
+/* Ensure the series header isn't broken. */
+#if (!defined(STM32_PCLK1)         ||     \
+     !defined(STM32_PCLK2)         ||     \
+     !defined(STM32_MCU_SERIES)    ||     \
+     !defined(STM32_NR_INTERRUPTS) ||     \
+     !defined(STM32_NR_GPIO_PORTS) ||     \
+     !defined(STM32_TIMER_MASK)    ||     \
+     !defined(STM32_DELAY_US_MULT) ||     \
+     !defined(STM32_SRAM_END)      ||     \
+     !defined(STM32_HAVE_DAC)      ||     \
+     !defined(STM32_HAVE_FSMC)     ||     \
+     !defined(STM32_HAVE_USB))
+#error "Bad STM32F1 configuration. Check <series/stm32.h> header for your MCU."
+#endif
+
+/*
+ * Derived macros
+ */
+
+/* FIXME [0.0.13] add this to ReST API page */
+/**
+ * @brief Statically determine whether a timer is present.
+ *
+ * Given a constant timer number n (starting from 1), this macro has a
+ * nonzero value exactly when TIMERn is available.
+ */
+#define STM32_HAVE_TIMER(n) (STM32_TIMER_MASK & (1 << (n)))
+
+/*
+ * Doxygen for functionality provided by series header.
+ */
+
+#ifdef __DOXYGEN__
+
+/*
+ * Clock configuration.
+ *
+ * These defines depend upon how the MCU is configured.  Because of
+ * the potential for a mismatch between them and the actual clock
+ * configuration, keep their number to a minimum.
+ */
+
+/**
+ * @brief APB1 clock speed, in Hz.
+ */
+#define STM32_PCLK1
+
+/**
+ *  @brief APB2 clock speed, in Hz.
+ */
+#define STM32_PCLK2
+
+/** @brief Deprecated. Use STM32_PCLK1 instead. */
+#define PCLK1
+/** @brief Deprecated. Use STM32_PCLK2 instead. */
+#define PCLK2
+
+/*
+ * Series- and MCU-specific values.
+ */
+
+/**
+ * @brief STM32 series value for the MCU being targeted.
+ *
+ * At time of writing, allowed values are: STM32_SERIES_F1,
+ * STM32_SERIES_F2. This set of values will expand as libmaple adds
+ * support for more STM32 series MCUs.
+ */
+#define STM32_MCU_SERIES
+
+/**
+ * @brief Number of interrupts in the vector table.
+ *
+ * This does not include Cortex-M interrupts (NMI, HardFault, etc.).
+ */
+#define STM32_NR_INTERRUPTS
+
+/**
+ * Number of GPIO ports.
+ */
+#define STM32_NR_GPIO_PORTS
+
+/* FIXME [0.0.13] add this to ReST API page */
+/**
+ * @brief Bitmask of timers available on the MCU.
+ *
+ * That is, if TIMERn is available, then STM32_TIMER_MASK & (1 << n)
+ * will be nonzero. For example, a nonzero value of "STM32_TIMER_MASK
+ * & 0x2" means TIMER1 is available.
+ *
+ * A bitmask is necessary as some STM32 MCUs have "holes" in the range
+ * of available timers.
+ */
+#define STM32_TIMER_MASK
+
+/**
+ * @brief Multiplier to convert microseconds into loop iterations
+ *        in delay_us().
+ *
+ * @see delay_us()
+ */
+#define STM32_DELAY_US_MULT
+
+/**
+ * @brief Pointer to end of built-in SRAM.
+ *
+ * Points to the address which is 1 byte past the last valid
+ * SRAM address.
+ */
+#define STM32_SRAM_END
+
+/**
+ * @brief 1 if the target MCU has a DAC, and 0 otherwise.
+ */
+#define STM32_HAVE_DAC
+
+/**
+ * @brief 1 if the target MCU has the FSMC peripheral, and 0 otherwise.
+ *
+ * Note that the feature set of the FSMC peripheral is restricted on
+ * some MCUs.
+ */
+#define STM32_HAVE_FSMC
+
+/**
+ * @brief 1 if the target MCU has a USB peripheral, and 0 otherwise.
+ *
+ * Note that a variety of USB peripherals are available across the
+ * different series, with widely varying feature sets and programming
+ * interfaces. This macro will be 1 if any such peripheral is present.
+ */
+#define STM32_HAVE_USB
+
+#endif  /* __DOXYGEN__ */
+
+/*
+ * The following are for backwards compatibility only.
+ */
+
+/* PCLK1 and PCLK2 are for backwards compatibility only; don't use in
+ * new code. */
+#ifndef PCLK1
+#define PCLK1 STM32_PCLK1
+#endif
+#if PCLK1 != STM32_PCLK1
+#error "PCLK1 (which is deprecated) differs from STM32_PCLK1."
+#endif
+#ifndef PCLK2
+#define PCLK2 STM32_PCLK2
+#endif
+#if PCLK2 != STM32_PCLK2
+#error "PCLK2 (which is deprecated) differs from STM32_PCLK2."
+#endif
+
+/** @brief Deprecated. Use STM32_NR_INTERRUPTS instead. */
+#define NR_INTERRUPTS                   STM32_NR_INTERRUPTS
+/** @brief Deprecated. Use STM32_NR_GPIO_PORTS instead. */
+#define NR_GPIO_PORTS                   STM32_NR_GPIO_PORTS
+/** @brief Deprecated. Use STM32_DELAY_US_MULT instead. */
+#define DELAY_US_MULT                   STM32_DELAY_US_MULT
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/include/libmaple/syscfg.h

@@ -0,0 +1,151 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/syscfg.h
+ * @brief System configuration controller (SYSCFG)
+ *
+ * Availability: STM32F2, STM32F4.
+ */
+
+#ifndef _LIBMAPLE_SYSCFG_H_
+#define _LIBMAPLE_SYSCFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Register map and base pointer
+ */
+
+/**
+ * @brief SYSCFG register map type.
+ */
+typedef struct syscfg_reg_map {
+    __io uint32 MEMRMP;    /**< Memory remap register */
+    __io uint32 PMC;       /**< Peripheral mode configuration */
+    __io uint32 EXTICR[4]; /**< External interrupt configuration registers */
+    const uint32 RESERVED1;
+    const uint32 RESERVED2;
+    __io uint32 CMPCR;   /**< Compensation cell control register */
+} syscfg_reg_map;
+
+/** SYSCFG register map base pointer */
+#define SYSCFG_BASE                     ((struct syscfg_reg_map*)0x40013800)
+
+/*
+ * Register bit definitions
+ */
+
+/* Memory remap register */
+
+#define SYSCFG_MEMRMP_MEM_MODE           0x3
+#define SYSCFG_MEMRMP_MEM_MODE_FLASH     0x0
+#define SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH 0x1
+#define SYSCFG_MEMRMP_MEM_MODE_FSMC_1    0x2
+#define SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM  0x3
+
+/* Peripheral mode configuration register */
+
+#define SYSCFG_PMC_MII_RMII_SEL_BIT     23
+
+#define SYSCFG_PMC_MII_RMII_SEL         (1U << SYSCFG_PMC_MII_RMII_SEL_BIT)
+#define SYSCFG_PMC_MII_RMII_SEL_MII     (0U << SYSCFG_PMC_MII_RMII_SEL_BIT)
+#define SYSCFG_PMC_MII_RMII_SEL_RMII    (1U << SYSCFG_PMC_MII_RMII_SEL_BIT)
+
+/* External interrupt configuration register 1 */
+
+#define SYSCFG_EXTICR1_EXTI0            0xF
+#define SYSCFG_EXTICR1_EXTI1            0xF0
+#define SYSCFG_EXTICR1_EXTI2            0xF00
+#define SYSCFG_EXTICR1_EXTI3            0xF000
+
+/* External interrupt configuration register 2 */
+
+#define SYSCFG_EXTICR2_EXTI4            0xF
+#define SYSCFG_EXTICR2_EXTI5            0xF0
+#define SYSCFG_EXTICR2_EXTI6            0xF00
+#define SYSCFG_EXTICR2_EXTI7            0xF000
+
+/* External interrupt configuration register 3 */
+
+#define SYSCFG_EXTICR3_EXTI8            0xF
+#define SYSCFG_EXTICR3_EXTI9            0xF0
+#define SYSCFG_EXTICR3_EXTI10           0xF00
+#define SYSCFG_EXTICR3_EXTI11           0xF000
+
+/* External interrupt configuration register 4 */
+
+#define SYSCFG_EXTICR4_EXTI12           0xF
+#define SYSCFG_EXTICR4_EXTI13           0xF0
+#define SYSCFG_EXTICR4_EXTI14           0xF00
+#define SYSCFG_EXTICR4_EXTI15           0xF000
+
+/* Compensation cell control register */
+
+#define SYSCFG_CMPCR_READY_BIT          8
+#define SYSCFG_CMPCR_CMP_PD_BIT         0
+
+#define SYSCFG_CMPCR_READY              (1U << SYSCFG_CMPCR_READY_BIT)
+#define SYSCFG_CMPCR_CMP_PD             (1U << SYSCFG_CMPCR_CMP_PD_BIT)
+#define SYSCFG_CMPCR_CMP_PD_PDWN        (0U << SYSCFG_CMPCR_CMP_PD_BIT)
+#define SYSCFG_CMPCR_CMP_PD_ENABLE      (1U << SYSCFG_CMPCR_CMP_PD_BIT)
+
+/*
+ * Routines
+ */
+
+void syscfg_init(void);
+
+void syscfg_enable_io_compensation(void);
+void syscfg_disable_io_compensation(void);
+
+/**
+ * @brief System memory mode
+ * These values specify what memory to map to address 0x00000000.
+ * @see syscfg_set_mem_mode
+ */
+typedef enum syscfg_mem_mode {
+    /** Main flash memory is mapped at 0x0. */
+    SYCFG_MEM_MODE_FLASH        = SYSCFG_MEMRMP_MEM_MODE_FLASH,
+    /** System flash (i.e. ST's baked-in bootloader) is mapped at 0x0. */
+    SYCFG_MEM_MODE_SYSTEM_FLASH = SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH,
+    /** FSMC bank 1 (NOR/PSRAM 1 and 2) is mapped at 0x0. */
+    SYCFG_MEM_MODE_FSMC_BANK_1  = SYSCFG_MEMRMP_MEM_MODE_FSMC_1,
+    /** Embedded SRAM (i.e., not backup SRAM) is mapped at 0x0. */
+    SYCFG_MEM_MODE_SRAM         = SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM,
+} syscfg_mem_mode;
+
+void syscfg_set_mem_mode(syscfg_mem_mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/systick.h → libmaple/include/libmaple/systick.h

@@ -25,21 +25,20 @@
  *****************************************************************************/
 
 /**
- * @file systick.h
- *
- * @brief Various system timer definitions
+ * @file libmaple/include/libmaple/systick.h
+ * @brief System timer definitions
  */
 
-#ifndef _SYSTICK_H_
-#define _SYSTICK_H_
-
-#include "libmaple_types.h"
-#include "util.h"
+#ifndef _LIBMAPLE_SYSTICK_H_
+#define _LIBMAPLE_SYSTICK_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple_types.h>
+#include <libmaple/util.h>
+
 /** SysTick register map type */
 typedef struct systick_reg_map {
     __io uint32 CSR;            /**< Control and status register */
@@ -114,4 +113,3 @@ static inline uint32 systick_check_underflow(void) {
 #endif
 
 #endif
-

libmaple/timer.h → libmaple/include/libmaple/timer.h

@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2011 LeafLabs, LLC.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,27 +25,26 @@
  *****************************************************************************/
 
 /**
- * @file   timer.h
+ * @file   libmaple/include/libmaple/timer.h
  * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief  New-style timer interface.
- *
- * Replaces old timers.h implementation.
+ * @brief  Timer interface.
  */
 
-#ifndef _TIMERS_H_
-#define _TIMERS_H_
-
-#include "libmaple.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "bitband.h"
+#ifndef _LIBMAPLE_TIMER_H_
+#define _LIBMAPLE_TIMER_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <series/timer.h>
+#include <libmaple/libmaple.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/bitband.h>
+
 /*
- * Register maps and devices
+ * Register maps
  */
 
 /** Advanced control timer register map type */
@@ -53,7 +52,7 @@ typedef struct timer_adv_reg_map {
     __io uint32 CR1;            /**< Control register 1 */
     __io uint32 CR2;            /**< Control register 2 */
     __io uint32 SMCR;           /**< Slave mode control register */
-    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 DIER;           /**< DMA/interrupt enable register */
     __io uint32 SR;             /**< Status register */
     __io uint32 EGR;            /**< Event generation register  */
     __io uint32 CCMR1;          /**< Capture/compare mode register 1 */
@@ -72,36 +71,17 @@ typedef struct timer_adv_reg_map {
     __io uint32 DMAR;           /**< DMA address for full transfer */
 } timer_adv_reg_map;
 
-/** General purpose timer register map type */
-typedef struct timer_gen_reg_map {
-    __io uint32 CR1;            /**< Control register 1 */
-    __io uint32 CR2;            /**< Control register 2 */
-    __io uint32 SMCR;           /**< Slave mode control register */
-    __io uint32 DIER;           /**< DMA/Interrupt enable register */
-    __io uint32 SR;             /**< Status register */
-    __io uint32 EGR;            /**< Event generation register  */
-    __io uint32 CCMR1;          /**< Capture/compare mode register 1 */
-    __io uint32 CCMR2;          /**< Capture/compare mode register 2 */
-    __io uint32 CCER;           /**< Capture/compare enable register */
-    __io uint32 CNT;            /**< Counter */
-    __io uint32 PSC;            /**< Prescaler */
-    __io uint32 ARR;            /**< Auto-reload register */
-    const uint32 RESERVED1;     /**< Reserved */
-    __io uint32 CCR1;           /**< Capture/compare register 1 */
-    __io uint32 CCR2;           /**< Capture/compare register 2 */
-    __io uint32 CCR3;           /**< Capture/compare register 3 */
-    __io uint32 CCR4;           /**< Capture/compare register 4 */
-    const uint32 RESERVED2;     /**< Reserved */
-    __io uint32 DCR;            /**< DMA control register */
-    __io uint32 DMAR;           /**< DMA address for full transfer */
-} timer_gen_reg_map;
+/* General purpose timer register map type: intentionally omitted.
+ *
+ * General purpose timers differ slightly across series, so leave it
+ * up to the series header to define struct timer_gen_reg_map. */
 
 /** Basic timer register map type */
 typedef struct timer_bas_reg_map {
     __io uint32 CR1;            /**< Control register 1 */
     __io uint32 CR2;            /**< Control register 2 */
     const uint32 RESERVED1;     /**< Reserved */
-    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 DIER;           /**< DMA/interrupt enable register */
     __io uint32 SR;             /**< Status register */
     __io uint32 EGR;            /**< Event generation register  */
     const uint32 RESERVED2;     /**< Reserved */
@@ -112,25 +92,6 @@ typedef struct timer_bas_reg_map {
     __io uint32 ARR;            /**< Auto-reload register */
 } timer_bas_reg_map;
 
-/** Timer 1 register map base pointer */
-#define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40012C00)
-/** Timer 2 register map base pointer */
-#define TIMER2_BASE        ((struct timer_gen_reg_map*)0x40000000)
-/** Timer 3 register map base pointer */
-#define TIMER3_BASE        ((struct timer_gen_reg_map*)0x40000400)
-/** Timer 4 register map base pointer */
-#define TIMER4_BASE        ((struct timer_gen_reg_map*)0x40000800)
-#ifdef STM32_HIGH_DENSITY
-/** Timer 5 register map base pointer */
-#define TIMER5_BASE        ((struct timer_gen_reg_map*)0x40000C00)
-/** Timer 6 register map base pointer */
-#define TIMER6_BASE        ((struct timer_bas_reg_map*)0x40001000)
-/** Timer 7 register map base pointer */
-#define TIMER7_BASE        ((struct timer_bas_reg_map*)0x40001400)
-/** Timer 8 register map base pointer */
-#define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40013400)
-#endif
-
 /*
  * Timer devices
  */
@@ -157,7 +118,7 @@ typedef union timer_reg_map {
 typedef enum timer_type {
     TIMER_ADVANCED,             /**< Advanced type */
     TIMER_GENERAL,              /**< General purpose type */
-    TIMER_BASIC                 /**< Basic type */
+    TIMER_BASIC,                /**< Basic type */
 } timer_type;
 
 /** Timer device type */
@@ -165,19 +126,54 @@ typedef struct timer_dev {
     timer_reg_map regs;         /**< Register map */
     rcc_clk_id clk_id;          /**< RCC clock information */
     timer_type type;            /**< Timer's type */
-    voidFuncPtr handlers[];     /**< User IRQ handlers */
+    voidFuncPtr handlers[];     /**<
+                                 * Don't touch these. Use these instead:
+                                 * @see timer_attach_interrupt()
+                                 * @see timer_detach_interrupt() */
 } timer_dev;
 
+#if STM32_HAVE_TIMER(1)
 extern timer_dev *TIMER1;
+#endif
+#if STM32_HAVE_TIMER(2)
 extern timer_dev *TIMER2;
+#endif
+#if STM32_HAVE_TIMER(3)
 extern timer_dev *TIMER3;
+#endif
+#if STM32_HAVE_TIMER(4)
 extern timer_dev *TIMER4;
-#ifdef STM32_HIGH_DENSITY
+#endif
+#if STM32_HAVE_TIMER(5)
 extern timer_dev *TIMER5;
+#endif
+#if STM32_HAVE_TIMER(6)
 extern timer_dev *TIMER6;
+#endif
+#if STM32_HAVE_TIMER(7)
 extern timer_dev *TIMER7;
+#endif
+#if STM32_HAVE_TIMER(8)
 extern timer_dev *TIMER8;
 #endif
+#if STM32_HAVE_TIMER(9)
+extern timer_dev *TIMER9;
+#endif
+#if STM32_HAVE_TIMER(10)
+extern timer_dev *TIMER10;
+#endif
+#if STM32_HAVE_TIMER(11)
+extern timer_dev *TIMER11;
+#endif
+#if STM32_HAVE_TIMER(12)
+extern timer_dev *TIMER12;
+#endif
+#if STM32_HAVE_TIMER(13)
+extern timer_dev *TIMER13;
+#endif
+#if STM32_HAVE_TIMER(14)
+extern timer_dev *TIMER14;
+#endif
 
 /*
  * Register bit definitions
@@ -196,17 +192,17 @@ extern timer_dev *TIMER8;
 #define TIMER_CR1_CKD_1TCKINT           (0x0 << 8)
 #define TIMER_CR1_CKD_2TCKINT           (0x1 << 8)
 #define TIMER_CR1_CKD_4TICKINT          (0x2 << 8)
-#define TIMER_CR1_ARPE                  BIT(TIMER_CR1_ARPE_BIT)
+#define TIMER_CR1_ARPE                  (1U << TIMER_CR1_ARPE_BIT)
 #define TIMER_CR1_CKD_CMS               (0x3 << 5)
 #define TIMER_CR1_CKD_CMS_EDGE          (0x0 << 5)
 #define TIMER_CR1_CKD_CMS_CENTER1       (0x1 << 5)
 #define TIMER_CR1_CKD_CMS_CENTER2       (0x2 << 5)
 #define TIMER_CR1_CKD_CMS_CENTER3       (0x3 << 5)
-#define TIMER_CR1_DIR                   BIT(TIMER_CR1_DIR_BIT)
-#define TIMER_CR1_OPM                   BIT(TIMER_CR1_OPM_BIT)
-#define TIMER_CR1_URS                   BIT(TIMER_CR1_URS_BIT)
-#define TIMER_CR1_UDIS                  BIT(TIMER_CR1_UDIS_BIT)
-#define TIMER_CR1_CEN                   BIT(TIMER_CR1_CEN_BIT)
+#define TIMER_CR1_DIR                   (1U << TIMER_CR1_DIR_BIT)
+#define TIMER_CR1_OPM                   (1U << TIMER_CR1_OPM_BIT)
+#define TIMER_CR1_URS                   (1U << TIMER_CR1_URS_BIT)
+#define TIMER_CR1_UDIS                  (1U << TIMER_CR1_UDIS_BIT)
+#define TIMER_CR1_CEN                   (1U << TIMER_CR1_CEN_BIT)
 
 /* Control register 2 (CR2) */
 
@@ -217,19 +213,19 @@ extern timer_dev *TIMER8;
 #define TIMER_CR2_OIS2_BIT              10
 #define TIMER_CR2_OIS1N_BIT             9
 #define TIMER_CR2_OIS1_BIT              8
-#define TIMER_CR2_TI1S_BIT              7 /* tills? yikes */
+#define TIMER_CR2_TI1S_BIT              7
 #define TIMER_CR2_CCDS_BIT              3
 #define TIMER_CR2_CCUS_BIT              2
 #define TIMER_CR2_CCPC_BIT              0
 
-#define TIMER_CR2_OIS4                  BIT(TIMER_CR2_OIS4_BIT)
-#define TIMER_CR2_OIS3N                 BIT(TIMER_CR2_OIS3N_BIT)
-#define TIMER_CR2_OIS3                  BIT(TIMER_CR2_OIS3_BIT)
-#define TIMER_CR2_OIS2N                 BIT(TIMER_CR2_OIS2N_BIT)
-#define TIMER_CR2_OIS2                  BIT(TIMER_CR2_OIS2_BIT)
-#define TIMER_CR2_OIS1N                 BIT(TIMER_CR2_OIS1N_BIT)
-#define TIMER_CR2_OIS1                  BIT(TIMER_CR2_OIS1_BIT)
-#define TIMER_CR2_TI1S                  BIT(TIMER_CR2_TI1S_BIT)
+#define TIMER_CR2_OIS4                  (1U << TIMER_CR2_OIS4_BIT)
+#define TIMER_CR2_OIS3N                 (1U << TIMER_CR2_OIS3N_BIT)
+#define TIMER_CR2_OIS3                  (1U << TIMER_CR2_OIS3_BIT)
+#define TIMER_CR2_OIS2N                 (1U << TIMER_CR2_OIS2N_BIT)
+#define TIMER_CR2_OIS2                  (1U << TIMER_CR2_OIS2_BIT)
+#define TIMER_CR2_OIS1N                 (1U << TIMER_CR2_OIS1N_BIT)
+#define TIMER_CR2_OIS1                  (1U << TIMER_CR2_OIS1_BIT)
+#define TIMER_CR2_TI1S                  (1U << TIMER_CR2_TI1S_BIT)
 #define TIMER_CR2_MMS                   (0x7 << 4)
 #define TIMER_CR2_MMS_RESET             (0x0 << 4)
 #define TIMER_CR2_MMS_ENABLE            (0x1 << 4)
@@ -239,9 +235,9 @@ extern timer_dev *TIMER8;
 #define TIMER_CR2_MMS_COMPARE_OC2REF    (0x5 << 4)
 #define TIMER_CR2_MMS_COMPARE_OC3REF    (0x6 << 4)
 #define TIMER_CR2_MMS_COMPARE_OC4REF    (0x7 << 4)
-#define TIMER_CR2_CCDS                  BIT(TIMER_CR2_CCDS_BIT)
-#define TIMER_CR2_CCUS                  BIT(TIMER_CR2_CCUS_BIT)
-#define TIMER_CR2_CCPC                  BIT(TIMER_CR2_CCPC_BIT)
+#define TIMER_CR2_CCDS                  (1U << TIMER_CR2_CCDS_BIT)
+#define TIMER_CR2_CCUS                  (1U << TIMER_CR2_CCUS_BIT)
+#define TIMER_CR2_CCPC                  (1U << TIMER_CR2_CCPC_BIT)
 
 /* Slave mode control register (SMCR) */
 
@@ -249,15 +245,15 @@ extern timer_dev *TIMER8;
 #define TIMER_SMCR_ECE_BIT              14
 #define TIMER_SMCR_MSM_BIT              7
 
-#define TIMER_SMCR_ETP                  BIT(TIMER_SMCR_ETP_BIT)
-#define TIMER_SMCR_ECE                  BIT(TIMER_SMCR_ECE_BIT)
+#define TIMER_SMCR_ETP                  (1U << TIMER_SMCR_ETP_BIT)
+#define TIMER_SMCR_ECE                  (1U << TIMER_SMCR_ECE_BIT)
 #define TIMER_SMCR_ETPS                 (0x3 << 12)
 #define TIMER_SMCR_ETPS_OFF             (0x0 << 12)
 #define TIMER_SMCR_ETPS_DIV2            (0x1 << 12)
 #define TIMER_SMCR_ETPS_DIV4            (0x2 << 12)
 #define TIMER_SMCR_ETPS_DIV8            (0x3 << 12)
 #define TIMER_SMCR_ETF                  (0xF << 12)
-#define TIMER_SMCR_MSM                  BIT(TIMER_SMCR_MSM_BIT)
+#define TIMER_SMCR_MSM                  (1U << TIMER_SMCR_MSM_BIT)
 #define TIMER_SMCR_TS                   (0x3 << 4)
 #define TIMER_SMCR_TS_ITR0              (0x0 << 4)
 #define TIMER_SMCR_TS_ITR1              (0x1 << 4)
@@ -280,30 +276,36 @@ extern timer_dev *TIMER8;
 /* DMA/Interrupt enable register (DIER) */
 
 #define TIMER_DIER_TDE_BIT              14
+#define TIMER_DIER_COMDE_BIT            13
 #define TIMER_DIER_CC4DE_BIT            12
 #define TIMER_DIER_CC3DE_BIT            11
 #define TIMER_DIER_CC2DE_BIT            10
 #define TIMER_DIER_CC1DE_BIT            9
 #define TIMER_DIER_UDE_BIT              8
+#define TIMER_DIER_BIE_BIT              7
 #define TIMER_DIER_TIE_BIT              6
+#define TIMER_DIER_COMIE_BIT            5
 #define TIMER_DIER_CC4IE_BIT            4
 #define TIMER_DIER_CC3IE_BIT            3
 #define TIMER_DIER_CC2IE_BIT            2
 #define TIMER_DIER_CC1IE_BIT            1
 #define TIMER_DIER_UIE_BIT              0
 
-#define TIMER_DIER_TDE                  BIT(TIMER_DIER_TDE_BIT)
-#define TIMER_DIER_CC4DE                BIT(TIMER_DIER_CC4DE_BIT)
-#define TIMER_DIER_CC3DE                BIT(TIMER_DIER_CC3DE_BIT)
-#define TIMER_DIER_CC2DE                BIT(TIMER_DIER_CC2DE_BIT)
-#define TIMER_DIER_CC1DE                BIT(TIMER_DIER_CC1DE_BIT)
-#define TIMER_DIER_UDE                  BIT(TIMER_DIER_UDE_BIT)
-#define TIMER_DIER_TIE                  BIT(TIMER_DIER_TIE_BIT)
-#define TIMER_DIER_CC4IE                BIT(TIMER_DIER_CC4IE_BIT)
-#define TIMER_DIER_CC3IE                BIT(TIMER_DIER_CC3IE_BIT)
-#define TIMER_DIER_CC2IE                BIT(TIMER_DIER_CC2IE_BIT)
-#define TIMER_DIER_CC1IE                BIT(TIMER_DIER_CC1IE_BIT)
-#define TIMER_DIER_UIE                  BIT(TIMER_DIER_UIE_BIT)
+#define TIMER_DIER_TDE                  (1U << TIMER_DIER_TDE_BIT)
+#define TIMER_DIER_COMDE                (1U << TIMER_DIER_COMDE_BIT)
+#define TIMER_DIER_CC4DE                (1U << TIMER_DIER_CC4DE_BIT)
+#define TIMER_DIER_CC3DE                (1U << TIMER_DIER_CC3DE_BIT)
+#define TIMER_DIER_CC2DE                (1U << TIMER_DIER_CC2DE_BIT)
+#define TIMER_DIER_CC1DE                (1U << TIMER_DIER_CC1DE_BIT)
+#define TIMER_DIER_UDE                  (1U << TIMER_DIER_UDE_BIT)
+#define TIMER_DIER_BIE                  (1U << TIMER_DIER_BIE_BIT)
+#define TIMER_DIER_TIE                  (1U << TIMER_DIER_TIE_BIT)
+#define TIMER_DIER_COMIE                (1U << TIMER_DIER_COMIE_BIT)
+#define TIMER_DIER_CC4IE                (1U << TIMER_DIER_CC4IE_BIT)
+#define TIMER_DIER_CC3IE                (1U << TIMER_DIER_CC3IE_BIT)
+#define TIMER_DIER_CC2IE                (1U << TIMER_DIER_CC2IE_BIT)
+#define TIMER_DIER_CC1IE                (1U << TIMER_DIER_CC1IE_BIT)
+#define TIMER_DIER_UIE                  (1U << TIMER_DIER_UIE_BIT)
 
 /* Status register (SR) */
 
@@ -320,34 +322,38 @@ extern timer_dev *TIMER8;
 #define TIMER_SR_CC1IF_BIT              1
 #define TIMER_SR_UIF_BIT                0
 
-#define TIMER_SR_CC4OF                  BIT(TIMER_SR_CC4OF_BIT)
-#define TIMER_SR_CC3OF                  BIT(TIMER_SR_CC3OF_BIT)
-#define TIMER_SR_CC2OF                  BIT(TIMER_SR_CC2OF_BIT)
-#define TIMER_SR_CC1OF                  BIT(TIMER_SR_CC1OF_BIT)
-#define TIMER_SR_BIF                    BIT(TIMER_SR_BIF_BIT)
-#define TIMER_SR_TIF                    BIT(TIMER_SR_TIF_BIT)
-#define TIMER_SR_COMIF                  BIT(TIMER_SR_COMIF_BIT)
-#define TIMER_SR_CC4IF                  BIT(TIMER_SR_CC4IF_BIT)
-#define TIMER_SR_CC3IF                  BIT(TIMER_SR_CC3IF_BIT)
-#define TIMER_SR_CC2IF                  BIT(TIMER_SR_CC2IF_BIT)
-#define TIMER_SR_CC1IF                  BIT(TIMER_SR_CC1IF_BIT)
-#define TIMER_SR_UIF                    BIT(TIMER_SR_UIF_BIT)
+#define TIMER_SR_CC4OF                  (1U << TIMER_SR_CC4OF_BIT)
+#define TIMER_SR_CC3OF                  (1U << TIMER_SR_CC3OF_BIT)
+#define TIMER_SR_CC2OF                  (1U << TIMER_SR_CC2OF_BIT)
+#define TIMER_SR_CC1OF                  (1U << TIMER_SR_CC1OF_BIT)
+#define TIMER_SR_BIF                    (1U << TIMER_SR_BIF_BIT)
+#define TIMER_SR_TIF                    (1U << TIMER_SR_TIF_BIT)
+#define TIMER_SR_COMIF                  (1U << TIMER_SR_COMIF_BIT)
+#define TIMER_SR_CC4IF                  (1U << TIMER_SR_CC4IF_BIT)
+#define TIMER_SR_CC3IF                  (1U << TIMER_SR_CC3IF_BIT)
+#define TIMER_SR_CC2IF                  (1U << TIMER_SR_CC2IF_BIT)
+#define TIMER_SR_CC1IF                  (1U << TIMER_SR_CC1IF_BIT)
+#define TIMER_SR_UIF                    (1U << TIMER_SR_UIF_BIT)
 
 /* Event generation register (EGR) */
 
+#define TIMER_EGR_BG_BIT                7
 #define TIMER_EGR_TG_BIT                6
+#define TIMER_EGR_COMG_BIT              5
 #define TIMER_EGR_CC4G_BIT              4
 #define TIMER_EGR_CC3G_BIT              3
 #define TIMER_EGR_CC2G_BIT              2
 #define TIMER_EGR_CC1G_BIT              1
 #define TIMER_EGR_UG_BIT                0
 
-#define TIMER_EGR_TG                    BIT(TIMER_EGR_TG_BIT)
-#define TIMER_EGR_CC4G                  BIT(TIMER_EGR_CC4G_BIT)
-#define TIMER_EGR_CC3G                  BIT(TIMER_EGR_CC3G_BIT)
-#define TIMER_EGR_CC2G                  BIT(TIMER_EGR_CC2G_BIT)
-#define TIMER_EGR_CC1G                  BIT(TIMER_EGR_CC1G_BIT)
-#define TIMER_EGR_UG                    BIT(TIMER_EGR_UG_BIT)
+#define TIMER_EGR_BG                    (1U << TIMER_EGR_BG_BIT)
+#define TIMER_EGR_TG                    (1U << TIMER_EGR_TG_BIT)
+#define TIMER_EGR_COMG                  (1U << TIMER_EGR_COMG_BIT)
+#define TIMER_EGR_CC4G                  (1U << TIMER_EGR_CC4G_BIT)
+#define TIMER_EGR_CC3G                  (1U << TIMER_EGR_CC3G_BIT)
+#define TIMER_EGR_CC2G                  (1U << TIMER_EGR_CC2G_BIT)
+#define TIMER_EGR_CC1G                  (1U << TIMER_EGR_CC1G_BIT)
+#define TIMER_EGR_UG                    (1U << TIMER_EGR_UG_BIT)
 
 /* Capture/compare mode registers, common values */
 
@@ -365,22 +371,22 @@ extern timer_dev *TIMER8;
 #define TIMER_CCMR1_OC1PE_BIT           3
 #define TIMER_CCMR1_OC1FE_BIT           2
 
-#define TIMER_CCMR1_OC2CE               BIT(TIMER_CCMR1_OC2CE_BIT)
+#define TIMER_CCMR1_OC2CE               (1U << TIMER_CCMR1_OC2CE_BIT)
 #define TIMER_CCMR1_OC2M                (0x3 << 12)
 #define TIMER_CCMR1_IC2F                (0xF << 12)
-#define TIMER_CCMR1_OC2PE               BIT(TIMER_CCMR1_OC2PE_BIT)
-#define TIMER_CCMR1_OC2FE               BIT(TIMER_CCMR1_OC2FE_BIT)
+#define TIMER_CCMR1_OC2PE               (1U << TIMER_CCMR1_OC2PE_BIT)
+#define TIMER_CCMR1_OC2FE               (1U << TIMER_CCMR1_OC2FE_BIT)
 #define TIMER_CCMR1_IC2PSC              (0x3 << 10)
 #define TIMER_CCMR1_CC2S                (0x3 << 8)
 #define TIMER_CCMR1_CC2S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
 #define TIMER_CCMR1_CC2S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
 #define TIMER_CCMR1_CC2S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
 #define TIMER_CCMR1_CC2S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
-#define TIMER_CCMR1_OC1CE               BIT(TIMER_CCMR1_OC1CE_BIT)
+#define TIMER_CCMR1_OC1CE               (1U << TIMER_CCMR1_OC1CE_BIT)
 #define TIMER_CCMR1_OC1M                (0x3 << 4)
 #define TIMER_CCMR1_IC1F                (0xF << 4)
-#define TIMER_CCMR1_OC1PE               BIT(TIMER_CCMR1_OC1PE_BIT)
-#define TIMER_CCMR1_OC1FE               BIT(TIMER_CCMR1_OC1FE_BIT)
+#define TIMER_CCMR1_OC1PE               (1U << TIMER_CCMR1_OC1PE_BIT)
+#define TIMER_CCMR1_OC1FE               (1U << TIMER_CCMR1_OC1FE_BIT)
 #define TIMER_CCMR1_IC1PSC              (0x3 << 2)
 #define TIMER_CCMR1_CC1S                0x3
 #define TIMER_CCMR1_CC1S_OUTPUT         TIMER_CCMR_CCS_OUTPUT
@@ -397,48 +403,60 @@ extern timer_dev *TIMER8;
 #define TIMER_CCMR2_OC3PE_BIT           3
 #define TIMER_CCMR2_OC3FE_BIT           2
 
-#define TIMER_CCMR2_OC4CE               BIT(TIMER_CCMR2_OC4CE_BIT)
+#define TIMER_CCMR2_OC4CE               (1U << TIMER_CCMR2_OC4CE_BIT)
 #define TIMER_CCMR2_OC4M                (0x3 << 12)
-#define TIMER_CCMR2_IC2F                (0xF << 12)
-#define TIMER_CCMR2_OC4PE               BIT(TIMER_CCMR2_OC4PE_BIT)
-#define TIMER_CCMR2_OC4FE               BIT(TIMER_CCMR2_OC4FE_BIT)
-#define TIMER_CCMR2_IC2PSC              (0x3 << 10)
+#define TIMER_CCMR2_IC4F                (0xF << 12)
+#define TIMER_CCMR2_OC4PE               (1U << TIMER_CCMR2_OC4PE_BIT)
+#define TIMER_CCMR2_OC4FE               (1U << TIMER_CCMR2_OC4FE_BIT)
+#define TIMER_CCMR2_IC4PSC              (0x3 << 10)
 #define TIMER_CCMR2_CC4S                (0x3 << 8)
-#define TIMER_CCMR1_CC4S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
-#define TIMER_CCMR1_CC4S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
-#define TIMER_CCMR1_CC4S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
-#define TIMER_CCMR1_CC4S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
-#define TIMER_CCMR2_OC3CE               BIT(TIMER_CCMR2_OC3CE_BIT)
+#define TIMER_CCMR2_CC4S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
+#define TIMER_CCMR2_CC4S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
+#define TIMER_CCMR2_CC4S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
+#define TIMER_CCMR2_CC4S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
+#define TIMER_CCMR2_OC3CE               (1U << TIMER_CCMR2_OC3CE_BIT)
 #define TIMER_CCMR2_OC3M                (0x3 << 4)
-#define TIMER_CCMR2_IC1F                (0xF << 4)
-#define TIMER_CCMR2_OC3PE               BIT(TIMER_CCMR2_OC3PE_BIT)
-#define TIMER_CCMR2_OC3FE               BIT(TIMER_CCMR2_OC3FE_BIT)
-#define TIMER_CCMR2_IC1PSC              (0x3 << 2)
+#define TIMER_CCMR2_IC3F                (0xF << 4)
+#define TIMER_CCMR2_OC3PE               (1U << TIMER_CCMR2_OC3PE_BIT)
+#define TIMER_CCMR2_OC3FE               (1U << TIMER_CCMR2_OC3FE_BIT)
+#define TIMER_CCMR2_IC3PSC              (0x3 << 2)
 #define TIMER_CCMR2_CC3S                0x3
-#define TIMER_CCMR1_CC3S_OUTPUT         TIMER_CCMR_CCS_OUTPUT
-#define TIMER_CCMR1_CC3S_INPUT_TI1      TIMER_CCMR_CCS_INPUT_TI1
-#define TIMER_CCMR1_CC3S_INPUT_TI2      TIMER_CCMR_CCS_INPUT_TI2
-#define TIMER_CCMR1_CC3S_INPUT_TRC      TIMER_CCMR_CCS_INPUT_TRC
+#define TIMER_CCMR2_CC3S_OUTPUT         TIMER_CCMR_CCS_OUTPUT
+#define TIMER_CCMR2_CC3S_INPUT_TI1      TIMER_CCMR_CCS_INPUT_TI1
+#define TIMER_CCMR2_CC3S_INPUT_TI2      TIMER_CCMR_CCS_INPUT_TI2
+#define TIMER_CCMR2_CC3S_INPUT_TRC      TIMER_CCMR_CCS_INPUT_TRC
 
 /* Capture/compare enable register (CCER) */
 
 #define TIMER_CCER_CC4P_BIT             13
 #define TIMER_CCER_CC4E_BIT             12
+#define TIMER_CCER_CC3NP_BIT            11
+#define TIMER_CCER_CC3NE_BIT            10
 #define TIMER_CCER_CC3P_BIT             9
 #define TIMER_CCER_CC3E_BIT             8
+#define TIMER_CCER_CC2NP_BIT            7
+#define TIMER_CCER_CC2NE_BIT            6
 #define TIMER_CCER_CC2P_BIT             5
 #define TIMER_CCER_CC2E_BIT             4
+#define TIMER_CCER_CC1NP_BIT            3
+#define TIMER_CCER_CC1NE_BIT            2
 #define TIMER_CCER_CC1P_BIT             1
 #define TIMER_CCER_CC1E_BIT             0
 
-#define TIMER_CCER_CC4P                 BIT(TIMER_CCER_CC4P_BIT)
-#define TIMER_CCER_CC4E                 BIT(TIMER_CCER_CC4E_BIT)
-#define TIMER_CCER_CC3P                 BIT(TIMER_CCER_CC3P_BIT)
-#define TIMER_CCER_CC3E                 BIT(TIMER_CCER_CC3E_BIT)
-#define TIMER_CCER_CC2P                 BIT(TIMER_CCER_CC2P_BIT)
-#define TIMER_CCER_CC2E                 BIT(TIMER_CCER_CC2E_BIT)
-#define TIMER_CCER_CC1P                 BIT(TIMER_CCER_CC1P_BIT)
-#define TIMER_CCER_CC1E                 BIT(TIMER_CCER_CC1E_BIT)
+#define TIMER_CCER_CC4P                 (1U << TIMER_CCER_CC4P_BIT)
+#define TIMER_CCER_CC4E                 (1U << TIMER_CCER_CC4E_BIT)
+#define TIMER_CCER_CC3NP                (1U << TIMER_CCER_CC3NP_BIT)
+#define TIMER_CCER_CC3NE                (1U << TIMER_CCER_CC3NE_BIT)
+#define TIMER_CCER_CC3P                 (1U << TIMER_CCER_CC3P_BIT)
+#define TIMER_CCER_CC3E                 (1U << TIMER_CCER_CC3E_BIT)
+#define TIMER_CCER_CC2NP                (1U << TIMER_CCER_CC2NP_BIT)
+#define TIMER_CCER_CC2NE                (1U << TIMER_CCER_CC2NE_BIT)
+#define TIMER_CCER_CC2P                 (1U << TIMER_CCER_CC2P_BIT)
+#define TIMER_CCER_CC2E                 (1U << TIMER_CCER_CC2E_BIT)
+#define TIMER_CCER_CC1NP                (1U << TIMER_CCER_CC1NP_BIT)
+#define TIMER_CCER_CC1NE                (1U << TIMER_CCER_CC1NE_BIT)
+#define TIMER_CCER_CC1P                 (1U << TIMER_CCER_CC1P_BIT)
+#define TIMER_CCER_CC1E                 (1U << TIMER_CCER_CC1E_BIT)
 
 /* Break and dead-time register (BDTR) */
 
@@ -449,12 +467,12 @@ extern timer_dev *TIMER8;
 #define TIMER_BDTR_OSSR_BIT             11
 #define TIMER_BDTR_OSSI_BIT             10
 
-#define TIMER_BDTR_MOE                  BIT(TIMER_BDTR_MOE_BIT)
-#define TIMER_BDTR_AOE                  BIT(TIMER_BDTR_AOE_BIT)
-#define TIMER_BDTR_BKP                  BIT(TIMER_BDTR_BKP_BIT)
-#define TIMER_BDTR_BKE                  BIT(TIMER_BDTR_BKE_BIT)
-#define TIMER_BDTR_OSSR                 BIT(TIMER_BDTR_OSSR_BIT)
-#define TIMER_BDTR_OSSI                 BIT(TIMER_BDTR_OSSI_BIT)
+#define TIMER_BDTR_MOE                  (1U << TIMER_BDTR_MOE_BIT)
+#define TIMER_BDTR_AOE                  (1U << TIMER_BDTR_AOE_BIT)
+#define TIMER_BDTR_BKP                  (1U << TIMER_BDTR_BKP_BIT)
+#define TIMER_BDTR_BKE                  (1U << TIMER_BDTR_BKE_BIT)
+#define TIMER_BDTR_OSSR                 (1U << TIMER_BDTR_OSSR_BIT)
+#define TIMER_BDTR_OSSI                 (1U << TIMER_BDTR_OSSI_BIT)
 #define TIMER_BDTR_LOCK                 (0x3 << 8)
 #define TIMER_BDTR_LOCK_OFF             (0x0 << 8)
 #define TIMER_BDTR_LOCK_LEVEL1          (0x1 << 8)
@@ -465,24 +483,24 @@ extern timer_dev *TIMER8;
 /* DMA control register (DCR) */
 
 #define TIMER_DCR_DBL                   (0x1F << 8)
-#define TIMER_DCR_DBL_1BYTE             (0x0 << 8)
-#define TIMER_DCR_DBL_2BYTE             (0x1 << 8)
-#define TIMER_DCR_DBL_3BYTE             (0x2 << 8)
-#define TIMER_DCR_DBL_4BYTE             (0x3 << 8)
-#define TIMER_DCR_DBL_5BYTE             (0x4 << 8)
-#define TIMER_DCR_DBL_6BYTE             (0x5 << 8)
-#define TIMER_DCR_DBL_7BYTE             (0x6 << 8)
-#define TIMER_DCR_DBL_8BYTE             (0x7 << 8)
-#define TIMER_DCR_DBL_9BYTE             (0x8 << 8)
-#define TIMER_DCR_DBL_10BYTE            (0x9 << 8)
-#define TIMER_DCR_DBL_11BYTE            (0xA << 8)
-#define TIMER_DCR_DBL_12BYTE            (0xB << 8)
-#define TIMER_DCR_DBL_13BYTE            (0xC << 8)
-#define TIMER_DCR_DBL_14BYTE            (0xD << 8)
-#define TIMER_DCR_DBL_15BYTE            (0xE << 8)
-#define TIMER_DCR_DBL_16BYTE            (0xF << 8)
-#define TIMER_DCR_DBL_17BYTE            (0x10 << 8)
-#define TIMER_DCR_DBL_18BYTE            (0x11 << 8)
+#define TIMER_DCR_DBL_1_XFER            (0x0 << 8)
+#define TIMER_DCR_DBL_2_XFER            (0x1 << 8)
+#define TIMER_DCR_DBL_3_XFER            (0x2 << 8)
+#define TIMER_DCR_DBL_4_XFER            (0x3 << 8)
+#define TIMER_DCR_DBL_5_XFER            (0x4 << 8)
+#define TIMER_DCR_DBL_6_XFER            (0x5 << 8)
+#define TIMER_DCR_DBL_7_XFER            (0x6 << 8)
+#define TIMER_DCR_DBL_8_XFER            (0x7 << 8)
+#define TIMER_DCR_DBL_9_XFER            (0x8 << 8)
+#define TIMER_DCR_DBL_10_XFER           (0x9 << 8)
+#define TIMER_DCR_DBL_11_XFER           (0xA << 8)
+#define TIMER_DCR_DBL_12_XFER           (0xB << 8)
+#define TIMER_DCR_DBL_13_XFER           (0xC << 8)
+#define TIMER_DCR_DBL_14_XFER           (0xD << 8)
+#define TIMER_DCR_DBL_15_XFER           (0xE << 8)
+#define TIMER_DCR_DBL_16_XFER           (0xF << 8)
+#define TIMER_DCR_DBL_17_XFER           (0x10 << 8)
+#define TIMER_DCR_DBL_18_XFER           (0x11 << 8)
 #define TIMER_DCR_DBA                   0x1F
 #define TIMER_DCR_DBA_CR1               0x0
 #define TIMER_DCR_DBA_CR2               0x1
@@ -510,27 +528,32 @@ extern timer_dev *TIMER8;
  */
 
 /**
- * Used to configure the behavior of a timer channel.  Note that not
- * all timers can be configured in every mode.
+ * @brief Used to configure the behavior of a timer channel.
+ *
+ * Be careful: not all timers can be configured in every mode.
  */
-/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */
 typedef enum timer_mode {
-    TIMER_DISABLED, /**< In this mode, the timer stops counting,
-                         channel interrupts are detached, and no state
-                         changes are output. */
-    TIMER_PWM, /**< PWM output mode. This is the default mode for pins
-                    after initialization. */
-    /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */
-    TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0
-                               to its reload value repeatedly; every
-                               time the counter value reaches one of
-                               the channel compare values, the
-                               corresponding interrupt is fired. */
-    /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */
-    /*                           pulse lengths of input signals. *\/ */
-    /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */
-    /*                      pulse on a GPIO pin for a specified amount of */
-    /*                      time. *\/ */
+    /**
+     * The timer stops counting, channel interrupts are detached, and
+     * no state changes are output. */
+    TIMER_DISABLED,
+
+    /** PWM output. */
+    TIMER_PWM,
+
+    /* TIMER_PWM_CENTER_ALIGNED, TODO: Center-aligned PWM output mode. */
+
+    /**
+     * The timer counts from 0 to its reload value repeatedly; every
+     * time the counter value reaches one of the channel compare
+     * values, the corresponding interrupt is fired. */
+    TIMER_OUTPUT_COMPARE,
+
+    /* TIMER_INPUT_CAPTURE, TODO: In this mode, the timer can measure the
+     *                            pulse lengths of input signals */
+    /* TIMER_ONE_PULSE, TODO: In this mode, the timer can generate a single
+     *                        pulse on a GPIO pin for a specified amount of
+     *                        time. */
 } timer_mode;
 
 /** Timer channel numbers */
@@ -555,27 +578,26 @@ void timer_init(timer_dev *dev);
 void timer_disable(timer_dev *dev);
 void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode);
 void timer_foreach(void (*fn)(timer_dev*));
+int timer_has_cc_channel(timer_dev *dev, uint8 channel);
 
 /**
  * @brief Timer interrupt number.
  *
- * Not all timers support all of these values; see the descriptions
- * for each value.
+ * Not all timers support all of these values. All timers support
+ * TIMER_UPDATE_INTERRUPT. "General purpose" timers can be a special
+ * nuisance in this regard, as they individually support different
+ * subsets of the available interupts. Consult your target's reference
+ * manual for the details.
  */
 typedef enum timer_interrupt_id {
-    TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */
-    TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available
-                              on general and advanced timers only. */
-    TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and
-                              advanced timers only. */
-    TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and
-                              advanced timers only. */
-    TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and
-                              advanced timers only. */
-    TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */
-    TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced
-                              timers only */
-    TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */
+    TIMER_UPDATE_INTERRUPT,     /**< Update interrupt. */
+    TIMER_CC1_INTERRUPT,        /**< Capture/compare 1 interrupt. */
+    TIMER_CC2_INTERRUPT,        /**< Capture/compare 2 interrupt. */
+    TIMER_CC3_INTERRUPT,        /**< Capture/compare 3 interrupt. */
+    TIMER_CC4_INTERRUPT,        /**< Capture/compare 4 interrupt. */
+    TIMER_COM_INTERRUPT,        /**< COM interrupt. */
+    TIMER_TRG_INTERRUPT,        /**< Trigger interrupt. */
+    TIMER_BREAK_INTERRUPT,      /**< Break interrupt. */
 } timer_interrupt_id;
 
 void timer_attach_interrupt(timer_dev *dev,
@@ -843,18 +865,19 @@ static inline void timer_cc_set_pol(timer_dev *dev, uint8 channel, uint8 pol) {
 /**
  * @brief Get a timer's DMA burst length.
  * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
- * @return Number of bytes to be transferred per DMA request, from 1 to 18.
+ * @return Number of transfers per read or write to timer DMA register,
+ *         from 1 to 18.
  */
 static inline uint8 timer_dma_get_burst_len(timer_dev *dev) {
     uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8;
-    return dbl + 1;             /* 0 means 1 byte, etc. */
+    return dbl + 1;             /* 0 means 1 transfer, etc. */
 }
 
 /**
  * @brief Set a timer's DMA burst length.
  * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
- * @param length DMA burst length; i.e., number of bytes to transfer
- *               per DMA request, from 1 to 18.
+ * @param length DMA burst length; i.e., number of DMA transfers per
+ *               read/write to timer DMA register, from 1 to 18.
  */
 static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) {
     uint32 tmp = (dev->regs).gen->DCR;
@@ -869,47 +892,52 @@ static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) {
  * Defines the base address for DMA transfers.
  */
 typedef enum timer_dma_base_addr {
-    TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */
-    TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */
-    TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode
-                                                   control register */
-    TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable
-                                                   register */
-    TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */
-    TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation
-                                                 register */
-    TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare
-                                                     mode register 1 */
-    TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare
-                                                     mode register 2 */
-    TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER,   /**< Base is capture/compare
-                                                     enable register */
-    TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT,     /**< Base is counter */
-    TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC,     /**< Base is prescaler */
-    TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR,     /**< Base is auto-reload
-                                                     register */
-    TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR,     /**< Base is repetition
-                                                     counter register */
-    TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1,   /**< Base is capture/compare
-                                                     register 1 */
-    TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2,   /**< Base is capture/compare
-                                                     register 2 */
-    TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3,   /**< Base is capture/compare
-                                                     register 3 */
-    TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4,   /**< Base is capture/compare
-                                                     register 4 */
-    TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR,   /**< Base is break and
-                                                     dead-time register */
-    TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR,     /**< Base is DMA control
-                                                     register */
-    TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR    /**< Base is DMA address for
-                                                     full transfer */
+    /** Base is control register 1 */
+    TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1,
+    /** Base is control register 2 */
+    TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2,
+    /** Base is slave mode control register */
+    TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR,
+    /** Base is DMA interrupt enable register */
+    TIMER_DMA_BASE_DIER  = TIMER_DCR_DBA_DIER,
+    /** Base is status register */
+    TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR,
+    /** Base is event generation register */
+    TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR,
+    /** Base is capture/compare mode register 1 */
+    TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1,
+    /** Base is capture/compare mode register 2 */
+    TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2,
+    /** Base is capture/compare enable register */
+    TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER,
+    /** Base is counter */
+    TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT,
+    /** Base is prescaler */
+    TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC,
+    /** Base is auto-reload register */
+    TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR,
+    /** Base is repetition counter register */
+    TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR,
+    /** Base is capture/compare register 1 */
+    TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1,
+    /** Base is capture/compare register 2 */
+    TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2,
+    /** Base is capture/compare register 3 */
+    TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3,
+    /** Base is capture/compare register 4 */
+    TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4,
+    /** Base is break and dead-time register */
+    TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR,
+    /** Base is DMA control register */
+    TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR,
+    /** Base is DMA address for full transfer */
+    TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR,
 } timer_dma_base_addr;
 
 /**
  * @brief Get the timer's DMA base address.
  *
- * Some restrictions apply; see ST RM0008.
+ * Some restrictions apply; see the reference manual for your chip.
  *
  * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
  * @return DMA base address
@@ -922,7 +950,7 @@ static inline timer_dma_base_addr timer_dma_get_base_addr(timer_dev *dev) {
 /**
  * @brief Set the timer's DMA base address.
  *
- * Some restrictions apply; see ST RM0008.
+ * Some restrictions apply; see the reference manual for your chip.
  *
  * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
  * @param dma_base DMA base address.
@@ -939,35 +967,38 @@ static inline void timer_dma_set_base_addr(timer_dev *dev,
  * Timer output compare modes.
  */
 typedef enum timer_oc_mode {
-    TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output
-                                      compare register and counter has no
-                                      effect on the outputs. */
-    TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced
-                                               high when the count matches
-                                               the channel capture/compare
-                                               register. */
-    TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced
-                                                 low when the counter matches
-                                                 the channel capture/compare
-                                                 register. */
-    TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter
-                                      matches the cannel capture/compare
-                                      register. */
-    TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */
-    TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */
-    TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1.  In upcounting, channel is
-                                     active as long as count is less than
-                                     channel capture/compare register, else
-                                     inactive.  In downcounting, channel is
-                                     inactive as long as count exceeds
-                                     capture/compare register, else
-                                     active. */
-    TIMER_OC_MODE_PWM_2 = 7 << 4  /**< PWM mode 2. In upcounting, channel is
-                                     inactive as long as count is less than
-                                     capture/compare register, else active.
-                                     In downcounting, channel is active as
-                                     long as count exceeds capture/compare
-                                     register, else inactive. */
+    /**
+     * Frozen: comparison between output compare register and counter
+     * has no effect on the outputs. */
+    TIMER_OC_MODE_FROZEN = 0 << 4,
+    /**
+     * OCxREF signal is forced high when the count matches the channel
+     * capture/compare register. */
+    TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4,
+    /**
+     * OCxREF signal is forced low when the counter matches the
+     * channel capture/compare register. */
+    TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4,
+    /**
+     * OCxREF toggles when counter matches the channel capture/compare
+     * register. */
+    TIMER_OC_MODE_TOGGLE = 3 << 4,
+    /** OCxREF is forced low. */
+    TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4,
+    /** OCxREF is forced high. */
+    TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4,
+    /**
+     * PWM mode 1.  In upcounting, channel is active as long as count
+     * is less than channel capture/compare register, else inactive.
+     * In downcounting, channel is inactive as long as count exceeds
+     * capture/compare register, else active. */
+    TIMER_OC_MODE_PWM_1 = 6 << 4,
+    /**
+     * PWM mode 2. In upcounting, channel is inactive as long as count
+     * is less than capture/compare register, else active.  In
+     * downcounting, channel is active as long as count exceeds
+     * capture/compare register, else inactive. */
+    TIMER_OC_MODE_PWM_2 = 7 << 4,
 } timer_oc_mode;
 
 /**
@@ -975,9 +1006,9 @@ typedef enum timer_oc_mode {
  * @see timer_oc_set_mode()
  */
 typedef enum timer_oc_mode_flags {
-    TIMER_OC_CE = BIT(7),       /**< Output compare clear enable. */
-    TIMER_OC_PE = BIT(3),       /**< Output compare preload enable. */
-    TIMER_OC_FE = BIT(2)        /**< Output compare fast enable. */
+    TIMER_OC_CE = 1U << 7,       /**< Output compare clear enable. */
+    TIMER_OC_PE = 1U << 3,       /**< Output compare preload enable. */
+    TIMER_OC_FE = 1U << 2,       /**< Output compare fast enable. */
 } timer_oc_mode_flags;
 
 /**
@@ -1005,6 +1036,73 @@ static inline void timer_oc_set_mode(timer_dev *dev,
     *ccmr = tmp;
 }
 
+/*
+ * Old, erroneous bit definitions from previous releases, kept for
+ * backwards compatibility:
+ */
+
+/** Deprecated. Use TIMER_CCMR1_CC4S_OUTPUT instead. */
+#define TIMER_CCMR1_CC4S_OUTPUT    TIMER_CCMR2_CC4S_OUTPUT
+/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI1 instead. */
+#define TIMER_CCMR1_CC4S_INPUT_TI1 TIMER_CCMR2_CC4S_INPUT_TI1
+/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI2 instead. */
+#define TIMER_CCMR1_CC4S_INPUT_TI2 TIMER_CCMR2_CC4S_INPUT_TI2
+/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TRC instead. */
+#define TIMER_CCMR1_CC4S_INPUT_TRC TIMER_CCMR2_CC4S_INPUT_TRC
+/** Deprecated. Use TIMER_CCMR2_IC4F instead. */
+#define TIMER_CCMR2_IC2F           TIMER_CCMR2_IC4F
+/** Deprecated. Use TIMER_CCMR2_IC4PSC instead. */
+#define TIMER_CCMR2_IC2PSC         TIMER_CCMR2_IC4PSC
+/** Deprecated. Use TIMER_CCMR2_IC3F instead. */
+#define TIMER_CCMR2_IC1F           TIMER_CCMR2_IC3F
+/** Deprecated. Use TIMER_CCMR2_IC3PSC instead. */
+#define TIMER_CCMR2_IC1PSC         TIMER_CCMR2_IC3PSC
+/** Deprecated. Use TIMER_CCMR1_CC3S_OUTPUT instead. */
+#define TIMER_CCMR1_CC3S_OUTPUT    TIMER_CCMR2_CC3S_OUTPUT
+/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI1 instead. */
+#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR2_CC3S_INPUT_TI1
+/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI2 instead. */
+#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR2_CC3S_INPUT_TI2
+/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TRC instead. */
+#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR2_CC3S_INPUT_TRC
+
+/** Deprecated. Use TIMER_DCR_DBL_1_XFER instead. */
+#define TIMER_DCR_DBL_1BYTE  TIMER_DCR_DBL_1_XFER
+/** Deprecated. Use TIMER_DCR_DBL_2_XFER instead. */
+#define TIMER_DCR_DBL_2BYTE  TIMER_DCR_DBL_2_XFER
+/** Deprecated. Use TIMER_DCR_DBL_3_XFER instead. */
+#define TIMER_DCR_DBL_3BYTE  TIMER_DCR_DBL_3_XFER
+/** Deprecated. Use TIMER_DCR_DBL_4_XFER instead. */
+#define TIMER_DCR_DBL_4BYTE  TIMER_DCR_DBL_4_XFER
+/** Deprecated. Use TIMER_DCR_DBL_5_XFER instead. */
+#define TIMER_DCR_DBL_5BYTE  TIMER_DCR_DBL_5_XFER
+/** Deprecated. Use TIMER_DCR_DBL_6_XFER instead. */
+#define TIMER_DCR_DBL_6BYTE  TIMER_DCR_DBL_6_XFER
+/** Deprecated. Use TIMER_DCR_DBL_7_XFER instead. */
+#define TIMER_DCR_DBL_7BYTE  TIMER_DCR_DBL_7_XFER
+/** Deprecated. Use TIMER_DCR_DBL_8_XFER instead. */
+#define TIMER_DCR_DBL_8BYTE  TIMER_DCR_DBL_8_XFER
+/** Deprecated. Use TIMER_DCR_DBL_9_XFER instead. */
+#define TIMER_DCR_DBL_9BYTE  TIMER_DCR_DBL_9_XFER
+/** Deprecated. Use TIMER_DCR_DBL_10_XFER instead. */
+#define TIMER_DCR_DBL_10BYTE TIMER_DCR_DBL_10_XFER
+/** Deprecated. Use TIMER_DCR_DBL_11_XFER instead. */
+#define TIMER_DCR_DBL_11BYTE TIMER_DCR_DBL_11_XFER
+/** Deprecated. Use TIMER_DCR_DBL_12_XFER instead. */
+#define TIMER_DCR_DBL_12BYTE TIMER_DCR_DBL_12_XFER
+/** Deprecated. Use TIMER_DCR_DBL_13_XFER instead. */
+#define TIMER_DCR_DBL_13BYTE TIMER_DCR_DBL_13_XFER
+/** Deprecated. Use TIMER_DCR_DBL_14_XFER instead. */
+#define TIMER_DCR_DBL_14BYTE TIMER_DCR_DBL_14_XFER
+/** Deprecated. Use TIMER_DCR_DBL_15_XFER instead. */
+#define TIMER_DCR_DBL_15BYTE TIMER_DCR_DBL_15_XFER
+/** Deprecated. Use TIMER_DCR_DBL_16_XFER instead. */
+#define TIMER_DCR_DBL_16BYTE TIMER_DCR_DBL_16_XFER
+/** Deprecated. Use TIMER_DCR_DBL_17_XFER instead. */
+#define TIMER_DCR_DBL_17BYTE TIMER_DCR_DBL_17_XFER
+/** Deprecated. Use TIMER_DCR_DBL_18_XFER instead. */
+#define TIMER_DCR_DBL_18BYTE TIMER_DCR_DBL_18_XFER
+
 #ifdef __cplusplus
 } // extern "C"
 #endif

libmaple/usart.h → libmaple/include/libmaple/usart.h

@@ -25,27 +25,28 @@
  *****************************************************************************/
 
 /**
- * @file usart.h
+ * @file libmaple/include/libmaple/usart.h
  * @author Marti Bolivar <mbolivar@leaflabs.com>,
  *         Perry Hung <perry@leaflabs.com>
  * @brief USART definitions and prototypes
  */
 
-#ifndef _USART_H_
-#define _USART_H_
-
-#include "libmaple_types.h"
-#include "util.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "ring_buffer.h"
+#ifndef _LIBMAPLE_USART_H_
+#define _LIBMAPLE_USART_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple_types.h>
+#include <libmaple/util.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/ring_buffer.h>
+#include <series/usart.h>
+
 /*
- * Register maps and devices
+ * Register map (common across supported STM32 series).
  */
 
 /** USART register map type */
@@ -59,169 +60,315 @@ typedef struct usart_reg_map {
     __io uint32 GTPR;           /**< Guard time and prescaler register */
 } usart_reg_map;
 
-/** USART1 register map base pointer */
-#define USART1_BASE                     ((struct usart_reg_map*)0x40013800)
-/** USART2 register map base pointer */
-#define USART2_BASE                     ((struct usart_reg_map*)0x40004400)
-/** USART3 register map base pointer */
-#define USART3_BASE                     ((struct usart_reg_map*)0x40004800)
-#ifdef STM32_HIGH_DENSITY
-/** UART4 register map base pointer */
-#define UART4_BASE                      ((struct usart_reg_map*)0x40004C00)
-/** UART5 register map base pointer */
-#define UART5_BASE                      ((struct usart_reg_map*)0x40005000)
-#endif
-
 /*
  * Register bit definitions
  */
 
 /* Status register */
 
+/** Clear to send bit */
 #define USART_SR_CTS_BIT                9
+/** Line break detection bit */
 #define USART_SR_LBD_BIT                8
+/** Transmit data register empty bit */
 #define USART_SR_TXE_BIT                7
+/** Transmission complete bit */
 #define USART_SR_TC_BIT                 6
+/** Read data register not empty bit */
 #define USART_SR_RXNE_BIT               5
+/** IDLE line detected bit */
 #define USART_SR_IDLE_BIT               4
+/** Overrun error bit */
 #define USART_SR_ORE_BIT                3
+/** Noise error bit */
 #define USART_SR_NE_BIT                 2
+/**
+ * @brief Synonym for USART_SR_NE_BIT.
+ *
+ * Some series (e.g. STM32F2) use "NF" for "noise flag" instead of the
+ * original "NE" for "noise error". The meaning of the bit is
+ * unchanged, but the NF flag can be disabled when the line is
+ * noise-free.
+ *
+ * @see USART_SR_NE_BIT
+ */
+#define USART_SR_NF_BIT                 USART_SR_NE_BIT
+/** Framing error bit */
 #define USART_SR_FE_BIT                 1
+/** Parity error bit */
 #define USART_SR_PE_BIT                 0
 
+/** Clear to send mask */
 #define USART_SR_CTS                    BIT(USART_SR_CTS_BIT)
+/** Line break detected mask */
 #define USART_SR_LBD                    BIT(USART_SR_LBD_BIT)
+/** Transmit data register empty mask */
 #define USART_SR_TXE                    BIT(USART_SR_TXE_BIT)
+/** Transmission complete mask */
 #define USART_SR_TC                     BIT(USART_SR_TC_BIT)
+/** Read data register not empty mask */
 #define USART_SR_RXNE                   BIT(USART_SR_RXNE_BIT)
+/** IDLE line detected mask */
 #define USART_SR_IDLE                   BIT(USART_SR_IDLE_BIT)
+/** Overrun error mask */
 #define USART_SR_ORE                    BIT(USART_SR_ORE_BIT)
+/** Noise error mask */
 #define USART_SR_NE                     BIT(USART_SR_NE_BIT)
+/**
+ * @brief Synonym for USART_SR_NE.
+ * @see USART_SR_NF_BIT
+ */
+#define USART_SR_NF                     USART_SR_NE
+/** Framing error mask */
 #define USART_SR_FE                     BIT(USART_SR_FE_BIT)
+/** Parity error mask */
 #define USART_SR_PE                     BIT(USART_SR_PE_BIT)
 
 /* Data register */
 
+/** Data register data value mask */
 #define USART_DR_DR                     0xFF
 
 /* Baud rate register */
 
+/** Mantissa of USARTDIV mask */
 #define USART_BRR_DIV_MANTISSA          (0xFFF << 4)
+/** Fraction of USARTDIV mask */
 #define USART_BRR_DIV_FRACTION          0xF
 
 /* Control register 1 */
 
+/** USART enable bit */
 #define USART_CR1_UE_BIT                13
+/** Word length bit */
 #define USART_CR1_M_BIT                 12
+/** Wakeup method bit */
 #define USART_CR1_WAKE_BIT              11
+/** Parity control enable bit */
 #define USART_CR1_PCE_BIT               10
+/** Parity selection bit */
 #define USART_CR1_PS_BIT                9
+/** Parity error interrupt enable bit */
 #define USART_CR1_PEIE_BIT              8
+/** Transmit data regsiter not empty interrupt enable bit */
 #define USART_CR1_TXEIE_BIT             7
+/** Transmission complete interrupt enable bit */
 #define USART_CR1_TCIE_BIT              6
+/** RXNE interrupt enable bit */
 #define USART_CR1_RXNEIE_BIT            5
+/** IDLE interrupt enable bit */
 #define USART_CR1_IDLEIE_BIT            4
+/** Transmitter enable bit */
 #define USART_CR1_TE_BIT                3
+/** Receiver enable bit */
 #define USART_CR1_RE_BIT                2
+/** Receiver wakeup bit */
 #define USART_CR1_RWU_BIT               1
+/** Send break bit */
 #define USART_CR1_SBK_BIT               0
 
+/** USART enable mask */
 #define USART_CR1_UE                    BIT(USART_CR1_UE_BIT)
+/** Word length mask */
 #define USART_CR1_M                     BIT(USART_CR1_M_BIT)
+/** Word length: 1 start bit, 8 data bits, n stop bit */
+#define USART_CR1_M_8N1                 (0 << USART_CR1_M_BIT)
+/** Word length: 1 start bit, 9 data bits, n stop bit */
+#define USART_CR1_M_9N1                 (1 << USART_CR1_M_BIT)
+/** Wakeup method mask */
 #define USART_CR1_WAKE                  BIT(USART_CR1_WAKE_BIT)
+/** Wakeup on idle line */
 #define USART_CR1_WAKE_IDLE             (0 << USART_CR1_WAKE_BIT)
+/** Wakeup on address mark */
 #define USART_CR1_WAKE_ADDR             (1 << USART_CR1_WAKE_BIT)
+/** Parity control enable mask */
 #define USART_CR1_PCE                   BIT(USART_CR1_PCE_BIT)
+/** Parity selection mask */
 #define USART_CR1_PS                    BIT(USART_CR1_PS_BIT)
+/** Parity selection: even parity */
 #define USART_CR1_PS_EVEN               (0 << USART_CR1_PS_BIT)
+/** Parity selection: odd parity */
 #define USART_CR1_PS_ODD                (1 << USART_CR1_PS_BIT)
+/** Parity error interrupt enable mask */
 #define USART_CR1_PEIE                  BIT(USART_CR1_PEIE_BIT)
+/** Transmit data register empty interrupt enable mask */
 #define USART_CR1_TXEIE                 BIT(USART_CR1_TXEIE_BIT)
+/** Transmission complete interrupt enable mask */
 #define USART_CR1_TCIE                  BIT(USART_CR1_TCIE_BIT)
+/** RXNE interrupt enable mask */
 #define USART_CR1_RXNEIE                BIT(USART_CR1_RXNEIE_BIT)
+/** IDLE line interrupt enable mask */
 #define USART_CR1_IDLEIE                BIT(USART_CR1_IDLEIE_BIT)
+/** Transmitter enable mask */
 #define USART_CR1_TE                    BIT(USART_CR1_TE_BIT)
+/** Receiver enable mask */
 #define USART_CR1_RE                    BIT(USART_CR1_RE_BIT)
+/** Receiver wakeup mask */
 #define USART_CR1_RWU                   BIT(USART_CR1_RWU_BIT)
+/** Receiver wakeup: receiver in active mode */
 #define USART_CR1_RWU_ACTIVE            (0 << USART_CR1_RWU_BIT)
+/** Receiver wakeup: receiver in mute mode */
 #define USART_CR1_RWU_MUTE              (1 << USART_CR1_RWU_BIT)
+/** Send break */
 #define USART_CR1_SBK                   BIT(USART_CR1_SBK_BIT)
 
 /* Control register 2 */
 
+/** LIN mode enable bit */
 #define USART_CR2_LINEN_BIT             14
+/** Clock enable bit */
 #define USART_CR2_CLKEN_BIT             11
+/** Clock polarity bit */
 #define USART_CR2_CPOL_BIT              10
+/** Clock phase bit */
 #define USART_CR2_CPHA_BIT              9
+/** Last bit clock pulse bit */
 #define USART_CR2_LBCL_BIT              8
+/** LIN break detection interrupt enable bit */
 #define USART_CR2_LBDIE_BIT             6
+/** LIN break detection length bit */
 #define USART_CR2_LBDL_BIT              5
 
+/** LIN mode enable mask */
 #define USART_CR2_LINEN                 BIT(USART_CR2_LINEN_BIT)
+/** STOP bits mask */
 #define USART_CR2_STOP                  (0x3 << 12)
+/** STOP bits: 1 stop bit */
 #define USART_CR2_STOP_BITS_1           (0x0 << 12)
-/* Not on UART4, UART5 */
+/**
+ * @brief STOP bits: 0.5 stop bits
+ * Not available  on UART4, UART5. */
 #define USART_CR2_STOP_BITS_POINT_5     (0x1 << 12)
-/* Not on UART4, UART5 */
-#define USART_CR2_STOP_BITS_1_POINT_5   (0x3 << 12)
+/** STOP bits: 2 stop bits */
 #define USART_CR2_STOP_BITS_2           (0x2 << 12)
+/**
+ * @brief STOP bits: 1.5 stop bits
+ * Not available  on UART4, UART5. */
+#define USART_CR2_STOP_BITS_1_POINT_5   (0x3 << 12)
+/**
+ * @brief Clock enable.
+ * Not available on UART4, UART5 */
 #define USART_CR2_CLKEN                 BIT(USART_CR2_CLKEN_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Clock polarity mask.
+ * Not available on UART4, UART5 */
 #define USART_CR2_CPOL                  BIT(USART_CR2_CPOL_BIT)
+/** Clock polarity: low */
 #define USART_CR2_CPOL_LOW              (0x0 << USART_CR2_CLKEN_BIT)
+/** Clock polarity: high */
 #define USART_CR2_CPOL_HIGH             (0x1 << USART_CR2_CLKEN_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Clock phase mask.
+ * Not available on UART4, UART5 */
 #define USART_CR2_CPHA                  BIT(USART_CR2_CPHA_BIT)
+/**
+ * @brief Clock phase: first
+ * First clock transition is the first data capture edge. */
 #define USART_CR2_CPHA_FIRST            (0x0 << USART_CR2_CPHA_BIT)
+/**
+ * @brief Clock phase: second
+ * Second clock transition is the first data capture edge. */
 #define USART_CR2_CPHA_SECOND           (0x1 << USART_CR2_CPHA_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Last bit clock pulse mask.
+ *
+ * When set, the last bit transmitted causes a clock pulse in
+ * synchronous mode.
+ *
+ * Not available on UART4, UART5 */
 #define USART_CR2_LBCL                  BIT(USART_CR2_LBCL_BIT)
+/** LIN break detection interrupt enable mask. */
 #define USART_CR2_LBDIE                 BIT(USART_CR2_LBDIE_BIT)
+/** LIN break detection length. */
 #define USART_CR2_LBDL                  BIT(USART_CR2_LBDL_BIT)
+/** LIN break detection length: 10 bits */
 #define USART_CR2_LBDL_10_BIT           (0 << USART_CR2_LBDL_BIT)
+/** LIN break detection length: 11 bits */
 #define USART_CR2_LBDL_11_BIT           (1 << USART_CR2_LBDL_BIT)
+/**
+ * @brief Address of the USART node
+ * This is useful during multiprocessor communication. */
 #define USART_CR2_ADD                   0xF
 
 /* Control register 3 */
 
+/** Clear to send interrupt enable bit */
 #define USART_CR3_CTSIE_BIT             10
+/** Clear to send enable bit */
 #define USART_CR3_CTSE_BIT              9
+/** Ready to send enable bit */
 #define USART_CR3_RTSE_BIT              8
+/** DMA enable transmitter bit */
 #define USART_CR3_DMAT_BIT              7
+/** DMA enable receiver bit */
 #define USART_CR3_DMAR_BIT              6
+/** Smartcard mode enable bit */
 #define USART_CR3_SCEN_BIT              5
+/** Smartcard NACK enable bit */
 #define USART_CR3_NACK_BIT              4
+/** Half-duplex selection bit */
 #define USART_CR3_HDSEL_BIT             3
+/** IrDA low power bit */
 #define USART_CR3_IRLP_BIT              2
+/** IrDA mode enable bit */
 #define USART_CR3_IREN_BIT              1
+/** Error interrupt enable bit */
 #define USART_CR3_EIE_BIT               0
 
-/* Not on UART4, UART5 */
+/**
+ * @brief Clear to send interrupt enable
+ * Not available on UART4, UART5. */
 #define USART_CR3_CTSIE                 BIT(USART_CR3_CTSIE_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Clear to send enable
+ * Not available on UART4, UART5. */
 #define USART_CR3_CTSE                  BIT(USART_CR3_CTSE_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Ready to send enable
+ * Not available on UART4, UART5. */
 #define USART_CR3_RTSE                  BIT(USART_CR3_RTSE_BIT)
-/* Not on UART5 */
+/**
+ * @brief DMA enable transmitter
+ * Not available on UART5. */
 #define USART_CR3_DMAT                  BIT(USART_CR3_DMAT_BIT)
-/* Not on UART5 */
+/**
+ * @brief DMA enable receiver
+ * Not available on UART5. */
 #define USART_CR3_DMAR                  BIT(USART_CR3_DMAR_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Smartcard mode enable
+ * Not available on UART4, UART5. */
 #define USART_CR3_SCEN                  BIT(USART_CR3_SCEN_BIT)
-/* Not on UART4, UART5 */
+/**
+ * @brief Smartcard NACK enable
+ * Not available on UART4, UART5. */
 #define USART_CR3_NACK                  BIT(USART_CR3_NACK_BIT)
+/**
+ * @brief Half-duplex selection
+ * When set, single-wire half duplex mode is selected.
+ */
 #define USART_CR3_HDSEL                 BIT(USART_CR3_HDSEL_BIT)
+/** IrDA low power mode */
 #define USART_CR3_IRLP                  BIT(USART_CR3_IRLP_BIT)
-#define USART_CR3_IRLP_NORMAL           (0 << USART_CR3_IRLP_BIT)
-#define USART_CR3_IRLP_LOW_POWER        (1 << USART_CR3_IRLP_BIT)
+/** IrDA mode: normal */
+#define USART_CR3_IRLP_NORMAL           (0U << USART_CR3_IRLP_BIT)
+/** IrDA mode: low power */
+#define USART_CR3_IRLP_LOW_POWER        (1U << USART_CR3_IRLP_BIT)
+/** IrDA mode enable */
 #define USART_CR3_IREN                  BIT(USART_CR3_IREN_BIT)
+/** Error interrupt enable */
 #define USART_CR3_EIE                   BIT(USART_CR3_EIE_BIT)
 
 /* Guard time and prescaler register */
 
-/* Not on UART4, UART5 */
+/**
+ * @brief Guard time value mask
+ * Used in Smartcard mode. Not available on UART4, UART5. */
 #define USART_GTPR_GT                   (0xFF << 8)
-/* Not on UART4, UART5 */
+/**
+ * @brief Prescaler value mask
+ * Restrictions on this value apply, depending on the USART mode. Not
+ * available on UART4, UART5. */
 #define USART_GTPR_PSC                  0xFF
 
 /*
@@ -236,7 +383,8 @@ typedef struct usart_reg_map {
 typedef struct usart_dev {
     usart_reg_map *regs;             /**< Register map */
     ring_buffer *rb;                 /**< RX ring buffer */
-    uint32 max_baud;                 /**< Maximum baud */
+    uint32 max_baud;                 /**< @brief Deprecated.
+                                      * Maximum baud rate. */
     uint8 rx_buf[USART_RX_BUF_SIZE]; /**< @brief Deprecated.
                                       * Actual RX buffer used by rb.
                                       * This field will be removed in
@@ -245,16 +393,27 @@ typedef struct usart_dev {
     nvic_irq_num irq_num;            /**< USART NVIC interrupt */
 } usart_dev;
 
-extern usart_dev *USART1;
-extern usart_dev *USART2;
-extern usart_dev *USART3;
-#ifdef STM32_HIGH_DENSITY
-extern usart_dev *UART4;
-extern usart_dev *UART5;
-#endif
-
 void usart_init(usart_dev *dev);
+
+struct gpio_dev;                /* forward declaration */
+/* FIXME [PRE 0.0.13] decide if flags are necessary */
+/**
+ * @brief Configure GPIOs for use as USART TX/RX.
+ * @param udev USART device to use
+ * @param rx_dev RX pin gpio_dev
+ * @param rx     RX pin bit on rx_dev
+ * @param tx_dev TX pin gpio_dev
+ * @param tx     TX pin bit on tx_dev
+ * @param flags  Currently ignored
+ */
+extern void usart_config_gpios_async(usart_dev *udev,
+                                     struct gpio_dev *rx_dev, uint8 rx,
+                                     struct gpio_dev *tx_dev, uint8 tx,
+                                     unsigned flags);
+
+#define USART_USE_PCLK 0
 void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud);
+
 void usart_enable(usart_dev *dev);
 void usart_disable(usart_dev *dev);
 void usart_foreach(void (*fn)(usart_dev *dev));
@@ -333,4 +492,4 @@ static inline void usart_reset_rx(usart_dev *dev) {
 } // extern "C"
 #endif
 
-#endif // _USART_H_
+#endif

libmaple/usb.h → libmaple/include/libmaple/usb.h

@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2010 LeafLabs LLC.
+ * Copyright (c) 2010, 2011 LeafLabs LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -28,16 +28,16 @@
  * NOTE: This API is _unstable_ and will change drastically over time.
  */
 
-#ifndef _USB_H_
-#define _USB_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
+#ifndef _LIBMAPLE_USB_H_
+#define _LIBMAPLE_USB_H_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+
 #ifndef USB_ISR_MSK
 /* Handle CTRM, WKUPM, SUSPM, ERRM, SOFM, ESOFM, RESETM */
 #define USB_ISR_MSK 0xBF00

libmaple/usb/usb_cdcacm.h → libmaple/include/libmaple/usb_cdcacm.h

@@ -25,15 +25,15 @@
  *****************************************************************************/
 
 /**
- * @file usb_cdcacm.h
+ * @file libmaple/include/libmaple/usb_cdcacm.h
  * @brief USB CDC ACM (virtual serial terminal) support
  */
 
-#ifndef _USB_CDCACM_H_
-#define _USB_CDCACM_H_
+#ifndef _LIBMAPLE_USB_CDCACM_H_
+#define _LIBMAPLE_USB_CDCACM_H_
 
-#include "libmaple_types.h"
-#include "gpio.h"
+#include <libmaple/libmaple_types.h>
+#include <libmaple/gpio.h>
 
 #ifdef __cplusplus
 extern "C" {

libmaple/util.h → libmaple/include/libmaple/util.h

@@ -25,30 +25,30 @@
  *****************************************************************************/
 
 /**
- * @file util.h
+ * @file libmaple/include/libmaple/util.h
  * @brief Miscellaneous utility macros and procedures.
  */
 
-#include "libmaple_types.h"
-
-#ifndef _UTIL_H_
-#define _UTIL_H_
+#ifndef _LIBMAPLE_UTIL_H_
+#define _LIBMAPLE_UTIL_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/libmaple_types.h>
+
 /*
  * Bit manipulation
  */
 
-/** 1 << the bit number */
+/** 1UL shifted left by 'shift' */
 #define BIT(shift)                     (1UL << (shift))
-/** Mask shifted left by 'shift' */
+/** 'Mask' shifted left by 'shift' */
 #define BIT_MASK_SHIFT(mask, shift)    ((mask) << (shift))
 /** Bits m to n of x */
 #define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m)))
-/** True if v is a power of two (1, 2, 4, 8, ...) */
+/** True iff v is a power of two (1, 2, 4, 8, ...) */
 #define IS_POWER_OF_TWO(v)  ((v) && !((v) & ((v) - 1)))
 
 /*

libmaple/iwdg.c

@@ -25,11 +25,11 @@
  *****************************************************************************/
 
 /**
- * @file iwdg.c
+ * @file libmaple/iwdg.c
  * @brief Independent watchdog (IWDG) support
  */
 
-#include "iwdg.h"
+#include <libmaple/iwdg.h>
 
 /**
  * @brief Initialise and start the watchdog

libmaple/nvic.c

@@ -25,13 +25,13 @@
  *****************************************************************************/
 
 /**
- * @file nvic.c
+ * @file libmaple/nvic.c
  * @brief Nested vector interrupt controller support.
  */
 
-#include "nvic.h"
-#include "scb.h"
-#include "stm32.h"
+#include <libmaple/nvic.h>
+#include <libmaple/scb.h>
+#include <libmaple/stm32.h>
 
 /**
  * @brief Set interrupt priority for an interrupt line
@@ -46,7 +46,7 @@
  */
 void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority) {
     if (irqn < 0) {
-        /* This interrupt is in the system handler block  */
+        /* This interrupt is in the system handler block */
         SCB_BASE->SHP[((uint32)irqn & 0xF) - 4] = (priority & 0xF) << 4;
     } else {
         NVIC_BASE->IP[irqn] = (priority & 0xF) << 4;
@@ -54,16 +54,12 @@ void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority) {
 }
 
 /**
- * @brief Initialize the NVIC
- * @param vector_table_address Vector table base address.
- * @param offset Offset from vector_table_address.  Some restrictions
- *               apply to the use of nonzero offsets; see ST RM0008
- *               and the ARM Cortex M3 Technical Reference Manual.
+ * @brief Initialize the NVIC, setting interrupts to a default priority.
  */
-void nvic_init(uint32 vector_table_address, uint32 offset) {
+void nvic_init(uint32 address, uint32 offset) {
     uint32 i;
 
-    nvic_set_vector_table(vector_table_address, offset);
+    nvic_set_vector_table(address, offset);
 
     /*
      * Lower priority level for all peripheral interrupts to lowest
@@ -78,10 +74,18 @@ void nvic_init(uint32 vector_table_address, uint32 offset) {
 }
 
 /**
- * Reset the vector table address.
+ * @brief Set the vector table base address.
+ *
+ * For stand-alone products, the vector table base address is normally
+ * the start of Flash (0x08000000).
+ *
+ * @param address Vector table base address.
+ * @param offset Offset from address.  Some restrictions apply to the
+ *               use of nonzero offsets; see the ARM Cortex M3
+ *               Technical Reference Manual.
  */
-void nvic_set_vector_table(uint32 addr, uint32 offset) {
-    SCB_BASE->VTOR = addr | (offset & 0x1FFFFF80);
+void nvic_set_vector_table(uint32 address, uint32 offset) {
+    SCB_BASE->VTOR = address | (offset & 0x1FFFFF80);
 }
 
 /**

libmaple/pwr.c

@@ -25,12 +25,12 @@
  *****************************************************************************/
 
 /**
- * @file pwr.c
+ * @file libmaple/pwr.c
  * @brief Power control (PWR) support.
  */
 
-#include "pwr.h"
-#include "rcc.h"
+#include <libmaple/pwr.h>
+#include <libmaple/rcc.h>
 
 /**
  * Enables the power interface clock, and resets the power device.

libmaple/rcc.c

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,182 +26,144 @@
  *****************************************************************************/
 
 /**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
+ * @file libmaple/rcc.c
+ * @brief Portable RCC routines.
  */
 
-#include "libmaple.h"
-#include "flash.h"
-#include "rcc.h"
-#include "bitband.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB                             RCC_AHB
-
-struct rcc_dev_info {
-    const rcc_clk_domain clk_domain;
-    const uint8 line_num;
-};
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-static const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
-    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
-    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
-    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
-    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
-    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
-    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
-    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
-    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
-    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
-    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
-    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
-    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
-    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
-    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
-    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
-    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
-    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
-    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
-    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
-    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
-    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
-    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
-    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
-    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
-    [RCC_USB]    = { .clk_domain = APB1, .line_num = 23},
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
-    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
-    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
-    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
-    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
-    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
-    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
-    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
-    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
-    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
-    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
-    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
-    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
-    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
-#endif
-#ifdef STM32_XL_DENSITY
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
-#endif
-};
+#include <libmaple/rcc.h>
+
+#include "rcc_private.h"
 
 /**
- * @brief Initialize the clock control system. Initializes the system
- *        clock source to use the PLL driven by an external oscillator
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
+ * @brief Get a peripheral's clock domain
+ * @param id Clock ID of the peripheral whose clock domain to return
+ * @return Clock source for the given clock ID
  */
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-    uint32 cfgr = 0;
-    uint32 cr;
-
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul;
-
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
-        ;
-
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
-        ;
+rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
+    return rcc_dev_table[id].clk_domain;
+}
 
-    /* Finally, let's switch over to the PLL */
+/**
+ * @brief Switch the clock used as the source of the system clock.
+ *
+ * After switching the source, this function blocks until the new
+ * clock source is in use.
+ *
+ * @param sysclk_src New system clock source.
+ * @see rcc_sysclk_src
+ */
+void rcc_switch_sysclk(rcc_sysclk_src sysclk_src) {
+    uint32 cfgr = RCC_BASE->CFGR;
     cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
+    cfgr |= sysclk_src;
+
+    /* Switch SYSCLK source. */
     RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
+
+    /* Wait for new source to come into use. */
+    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != (sysclk_src << 2))
         ;
 }
 
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
+/*
+ * Turning clocks off and on, querying their status.
  */
-void rcc_clk_enable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 1);
+
+/* IMPORTANT NOTE FOR IMPLEMENTORS:
+ *
+ * libmaple assumes that enum rcc_clk enumerators are two-byte
+ * values, stored in a uint16, in the following way:
+ *
+ *  - The high-order byte is the byte offset (from RCC_BASE) of the register
+ *    to touch when turning on or off the given clock.
+ *
+ *  - The low-order byte is the bit in that register that turns the
+ *    clock on or off.
+ *
+ * Example for STM32F1: Turning on the high-speed external clock (HSE)
+ * involves setting HSEON, bit 16, of RCC_CR. The high-order byte is
+ * then offsetof(struct rcc_reg_map, CR) = 0, and the low-order byte
+ * is 16.
+ *
+ * The corresponding value of RCC_CLK_HSE is thus (0 << 8) | 16 = 16.
+ *
+ * On all known STM32 series, this encoding has the property that
+ * adding one to the low byte also gives the bit to check to determine
+ * if the clock is ready. For example, on STM32F1, RCC_CR_HSERDY is
+ * bit 17. If that's not the case on your series, rcc_is_clk_ready()
+ * won't work for you. */
+
+/* Returns the RCC register which controls the clock source. */
+static inline __io uint32* rcc_clk_reg(rcc_clk clock) {
+    return (__io uint32*)((__io uint8*)RCC_BASE + (clock >> 8));
+}
+
+/* Returns a mask in rcc_clk_reg(clock) to be used for turning the
+ * clock on and off */
+static inline uint32 rcc_clk_on_mask(rcc_clk clock) {
+    return 1 << (clock & 0xFF);
+}
+
+/* Returns a mask in rcc_clk_reg(clock) to be used when checking the
+ * readiness of the clock. */
+static inline uint32 rcc_clk_ready_mask(rcc_clk clock) {
+    return rcc_clk_on_mask(clock) << 1;
 }
 
 /**
- * @brief Reset a peripheral.
- * @param id Clock ID of the peripheral to reset.
+ * @brief Turn on a clock source.
+ *
+ * After this routine exits, callers should ensure that the clock
+ * source is ready by waiting until rcc_is_clk_ready(clock) returns
+ * true.
+ *
+ * @param clock Clock to turn on.
+ * @see rcc_turn_off_clk()
+ * @see rcc_is_clk_ready()
  */
-void rcc_reset_dev(rcc_clk_id id) {
-    static const __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io void* addr = (__io void*)reset_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(addr, lnum, 1);
-    bb_peri_set_bit(addr, lnum, 0);
+void rcc_turn_on_clk(rcc_clk clock) {
+    *rcc_clk_reg(clock) |= rcc_clk_on_mask(clock);
 }
 
 /**
- * @brief Get a peripheral's clock domain
- * @param id Clock ID of the peripheral whose clock domain to return
- * @return Clock source for the given clock ID
+ * @brief Turn off a clock source.
+ *
+ * In certain configurations, certain clock sources cannot be safely
+ * turned off. (For example, the main PLL on STM32F1 devices cannot be
+ * turned off if it has been selected as the SYSCLK source). Consult
+ * the reference material for your MCU to ensure it is safe to call
+ * this function.
+ *
+ * @param clock Clock to turn off.
+ * @see rcc_turn_on_clk()
+ * @see rcc_is_clk_ready()
  */
-rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
-    return rcc_dev_table[id].clk_domain;
+void rcc_turn_off_clk(rcc_clk clock) {
+    *rcc_clk_reg(clock) &= ~rcc_clk_on_mask(clock);
 }
 
 /**
- * @brief Set the divider on a peripheral prescaler
- * @param prescaler prescaler to set
- * @param divider prescaler divider
+ * @brief Check if a clock is on.
+ * @param clock Clock to check.
+ * @return 1 if the clock is on, 0 if the clock is off.
  */
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
+int rcc_is_clk_on(rcc_clk clock) {
+    return !!(*rcc_clk_reg(clock) & rcc_clk_on_mask(clock));
+}
 
-    uint32 cfgr = RCC_BASE->CFGR;
-    cfgr &= ~masks[prescaler];
-    cfgr |= divider;
-    RCC_BASE->CFGR = cfgr;
+/**
+ * @brief Check if a clock source is ready.
+ *
+ * In general, it is not safe to rely on a clock source unless this
+ * function returns nonzero. Also note that this function may return
+ * nonzero for a short period of time after a clock has been turned
+ * off. Consult the reference material for your MCU for more details.
+ *
+ * @param clock Clock whose readiness to check for.
+ * @return Nonzero if the clock is ready, zero otherwise.
+ * @see rcc_turn_on_clk()
+ * @see rcc_turn_off_clk()
+ */
+int rcc_is_clk_ready(rcc_clk clock) {
+    return (int)(*rcc_clk_reg(clock) & rcc_clk_ready_mask(clock));
 }

libmaple/rcc_private.h

@@ -0,0 +1,67 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * RCC private header.
+ */
+
+#ifndef _LIBMAPLE_PRIVATE_RCC_H_
+#define _LIBMAPLE_PRIVATE_RCC_H_
+
+#include <libmaple/bitband.h>
+
+struct rcc_dev_info {
+    const rcc_clk_domain clk_domain;
+    const uint8 line_num;
+};
+
+extern const struct rcc_dev_info rcc_dev_table[];
+
+static inline void rcc_do_clk_enable(__io uint32** enable_regs,
+                                     rcc_clk_id id) {
+    __io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
+    uint8 line_num = rcc_dev_table[id].line_num;
+    bb_peri_set_bit(enable_reg, line_num, 1);
+}
+
+static inline void rcc_do_reset_dev(__io uint32** reset_regs,
+                                    rcc_clk_id id) {
+    __io uint32 *reset_reg = reset_regs[rcc_dev_clk(id)];
+    uint8 line_num = rcc_dev_table[id].line_num;
+    bb_peri_set_bit(reset_reg, line_num, 1);
+    bb_peri_set_bit(reset_reg, line_num, 0);
+}
+
+static inline void rcc_do_set_prescaler(const uint32 *masks,
+                                        rcc_prescaler prescaler,
+                                        uint32 divider) {
+    uint32 cfgr = RCC_BASE->CFGR;
+    cfgr &= ~masks[prescaler];
+    cfgr |= divider;
+    RCC_BASE->CFGR = cfgr;
+}
+
+#endif

libmaple/rules.mk

@@ -3,43 +3,35 @@ sp              := $(sp).x
 dirstack_$(sp)  := $(d)
 d               := $(dir)
 BUILDDIRS       += $(BUILD_PATH)/$(d)
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb/usb_lib
 
-LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usb -I$(LIBMAPLE_PATH)/usb/usb_lib
+LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -I$(LIBMAPLE_MODULE_SERIES)/include
+LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH)
 
 # Local flags
-CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror
+CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror
 
 # Local rules and targets
-cSRCS_$(d) := adc.c                    \
-              bkp.c                    \
-              dac.c                    \
-              dma.c                    \
-              exti.c                   \
-              flash.c                  \
-              fsmc.c                   \
-              gpio.c                   \
-              iwdg.c                   \
-              nvic.c                   \
-              pwr.c		       \
-              i2c.c                    \
-              rcc.c                    \
-              spi.c                    \
-              syscalls.c               \
-              systick.c                \
-              timer.c                  \
-              usart.c                  \
-              util.c                   \
-              usb/usb.c                \
-              usb/usb_reg_map.c        \
-              usb/usb_cdcacm.c         \
-              usb/usb_lib/usb_core.c   \
-              usb/usb_lib/usb_init.c   \
-              usb/usb_lib/usb_mem.c    \
-              usb/usb_lib/usb_regs.c
-
+cSRCS_$(d) := adc.c
+cSRCS_$(d) += dac.c
+cSRCS_$(d) += dma.c
+cSRCS_$(d) += exti.c
+cSRCS_$(d) += flash.c
+cSRCS_$(d) += gpio.c
+cSRCS_$(d) += iwdg.c
+cSRCS_$(d) += nvic.c
+cSRCS_$(d) += pwr.c
+cSRCS_$(d) += rcc.c
+cSRCS_$(d) += spi.c
+cSRCS_$(d) += systick.c
+cSRCS_$(d) += timer.c
+cSRCS_$(d) += usart.c
+cSRCS_$(d) += usart_private.c
+cSRCS_$(d) += util.c
 sSRCS_$(d) := exc.S
+# I2C support must be ported to F2:
+ifeq ($(MCU_SERIES),stm32f1)
+cSRCS_$(d) += i2c.c
+endif
 
 cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
 sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%)

libmaple/spi.c

@@ -1,6 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  * Copyright (c) 2010 Perry Hung.
  *
  * Permission is hereby granted, free of charge, to any person
@@ -25,48 +26,18 @@
  *****************************************************************************/
 
 /**
- * @file spi.c
+ * @file libmaple/spi.c
  * @author Marti Bolivar <mbolivar@leaflabs.com>
  * @brief Serial Peripheral Interface (SPI) support.
  *        Currently, there is no Integrated Interchip Sound (I2S) support.
  */
 
-#include "spi.h"
-#include "bitband.h"
+#include <libmaple/spi.h>
+#include <libmaple/bitband.h>
 
 static void spi_reconfigure(spi_dev *dev, uint32 cr1_config);
 
 /*
- * SPI devices
- */
-
-static spi_dev spi1 = {
-    .regs     = SPI1_BASE,
-    .clk_id   = RCC_SPI1,
-    .irq_num  = NVIC_SPI1,
-};
-/** SPI device 1 */
-spi_dev *SPI1 = &spi1;
-
-static spi_dev spi2 = {
-    .regs     = SPI2_BASE,
-    .clk_id   = RCC_SPI2,
-    .irq_num  = NVIC_SPI2,
-};
-/** SPI device 2 */
-spi_dev *SPI2 = &spi2;
-
-#ifdef STM32_HIGH_DENSITY
-static spi_dev spi3 = {
-    .regs     = SPI3_BASE,
-    .clk_id   = RCC_SPI3,
-    .irq_num  = NVIC_SPI3,
-};
-/** SPI device 3 */
-spi_dev *SPI3 = &spi3;
-#endif
-
-/*
  * SPI convenience routines
  */
 
@@ -80,37 +51,6 @@ void spi_init(spi_dev *dev) {
 }
 
 /**
- * @brief Configure GPIO bit modes for use as a SPI port's pins.
- * @param as_master If true, configure bits for use as a bus master.
- *                  Otherwise, configure bits for use as slave.
- * @param nss_dev NSS pin's GPIO device
- * @param comm_dev SCK, MISO, MOSI pins' GPIO device
- * @param nss_bit NSS pin's GPIO bit on nss_dev
- * @param sck_bit SCK pin's GPIO bit on comm_dev
- * @param miso_bit MISO pin's GPIO bit on comm_dev
- * @param mosi_bit MOSI pin's GPIO bit on comm_dev
- */
-void spi_gpio_cfg(uint8 as_master,
-                  gpio_dev *nss_dev,
-                  uint8 nss_bit,
-                  gpio_dev *comm_dev,
-                  uint8 sck_bit,
-                  uint8 miso_bit,
-                  uint8 mosi_bit) {
-    if (as_master) {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
-    } else {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING);
-    }
-}
-
-/**
  * @brief Configure and enable a SPI device as bus master.
  *
  * The device's peripheral will be disabled before being reconfigured.
@@ -165,18 +105,6 @@ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
 }
 
 /**
- * @brief Call a function on each SPI port
- * @param fn Function to call.
- */
-void spi_foreach(void (*fn)(spi_dev*)) {
-    fn(SPI1);
-    fn(SPI2);
-#ifdef STM32_HIGH_DENSITY
-    fn(SPI3);
-#endif
-}
-
-/**
  * @brief Enable a SPI peripheral
  * @param dev Device to enable
  */
@@ -234,7 +162,3 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
     dev->regs->CR1 = cr1_config;
     spi_peripheral_enable(dev);
 }
-
-/*
- * IRQ handlers (TODO)
- */

libmaple/spi_private.h

@@ -0,0 +1,37 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifndef _LIBMAPLE_SPI_PRIVATE_H_
+#define _LIBMAPLE_SPI_PRIVATE_H_
+
+#define SPI_DEV(num)                              \
+    {                                             \
+        .regs    = SPI##num##_BASE,               \
+        .clk_id  = RCC_SPI##num,                  \
+        .irq_num = NVIC_SPI##num,                 \
+    }
+
+#endif

libmaple/stm32.h

@@ -1,191 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file stm32.h
- * @brief STM32 chip-specific definitions
- */
-
-#ifndef _STM32_H_
-#define _STM32_H_
-
-/*
- * User-specific configuration.
- *
- * The #defines here depend upon how libmaple is used.  Because of the
- * potential for a mismatch between them and the actual libmaple
- * usage, you should try to keep their number to an absolute minimum.
- */
-
-#ifdef __DOXYGEN_PREDEFINED_HACK
-
-    /** @brief APB1 clock speed, in Hz. */
-    #define STM32_PCLK1
-    /** @brief APB2 clock speed, in Hz. */
-    #define STM32_PCLK2
-
-    /** Deprecated.  Use STM32_PCLK1 instead. */
-    #define PCLK1
-    /** Deprecated. Use STM32_PCLK2 instead. */
-    #define PCLK2
-
-#endif
-
-#ifndef STM32_PCLK1
-#define STM32_PCLK1   36000000U
-#endif
-#ifndef PCLK1
-#define PCLK1 STM32_PCLK1
-#endif
-#if PCLK1 != STM32_PCLK1
-#error "(Deprecated) PCLK1 differs from STM32_PCLK1"
-#endif
-
-#ifndef STM32_PCLK2
-#define STM32_PCLK2   72000000U
-#endif
-#ifndef PCLK2
-#define PCLK2 STM32_PCLK2
-#endif
-#if PCLK2 != STM32_PCLK2
-#error "(Deprecated) PCLK2 differs from STM32_PCLK2"
-#endif
-
-/*
- * Density-specific configuration.
- */
-
-#ifdef __DOXYGEN_PREDEFINED_HACK
-
-    /**
-     * @brief Number of interrupts in the NVIC.
-     *
-     * This define is automatically generated whenever the proper
-     * density is defined (currently, this is restricted to defining
-     * one of STM32_MEDIUM_DENSITY and STM32_HIGH_DENSITY).
-     */
-    #define STM32_NR_INTERRUPTS
-
-    /** Deprecated.  Use STM32_NR_INTERRUPTS instead. */
-    #define NR_INTERRUPTS
-
-#endif
-
-#ifdef STM32_MEDIUM_DENSITY
-    #define STM32_NR_INTERRUPTS 43
-#elif defined(STM32_HIGH_DENSITY)
-    #define STM32_NR_INTERRUPTS 60
-#else
-#error "No STM32 board type defined!"
-#endif
-
-#define NR_INTERRUPTS STM32_NR_INTERRUPTS
-
-/*
- * MCU-specific configuration.
- */
-
-#ifdef __DOXYGEN_PREDEFINED_HACK
-
-    /**
-     * Number of GPIO ports.
-     */
-    #define STM32_NR_GPIO_PORTS
-
-    /**
-     * @brief Multiplier to convert microseconds into loop iterations
-     *        in delay_us().
-     *
-     * @see delay_us()
-     */
-    #define STM32_DELAY_US_MULT
-
-    /**
-     * @brief Pointer to end of built-in SRAM.
-     *
-     * Points to the address which is 1 byte past the last valid
-     * SRAM address.
-     */
-    #define STM32_SRAM_END
-
-    /** Deprecated.  Use STM32_NR_GPIO_PORTS instead. */
-    #define NR_GPIO_PORTS
-    /** Deprecated.  Use STM32_DELAY_US_MULT instead. */
-    #define DELAY_US_MULT
-
-#endif
-
-#if defined(MCU_STM32F103RB)
-    /* e.g., LeafLabs Maple */
-
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103ZE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          7
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103CB)
-    /* e.g., LeafLabs Maple Mini */
-
-    /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true.
-     * But only pins 0 and 1 exist, and they're used for OSC on the
-     * Mini, so we'll live with this for now. */
-    #define STM32_NR_GPIO_PORTS          3
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103RE)
-    /* e.g., LeafLabs Maple RET6 edition */
-
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#else
-
-#error "No MCU type specified. Add something like -DMCU_STM32F103RB "   \
-       "to your compiler arguments (probably in a Makefile)."
-
-#endif
-
-#endif  /* _STM32_H_ */

libmaple/stm32_private.h

@@ -0,0 +1,45 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+#ifndef _LIBMAPLE_STM32_PRIVATE_H_
+#define _LIBMAPLE_STM32_PRIVATE_H_
+
+typedef enum stm32_mem_block_purpose {
+    STM32_BLOCK_CODE,
+    STM32_BLOCK_SRAM,
+    STM32_BLOCK_PERIPH,
+    STM32_BLOCK_FSMC_1_2,
+    STM32_BLOCK_FSMC_3_4,
+    STM32_BLOCK_FSMC_REG,
+    STM32_BLOCK_UNUSED,
+    STM32_BLOCK_CORTEX_INTERNAL,
+} stm32_mem_block_purpose;
+
+static inline stm32_mem_block_purpose stm32_block_purpose(void *addr) {
+    return (stm32_mem_block_purpose)((unsigned)addr >> 29);
+}
+
+#endif

libmaple/stm32f1/adc.c

@@ -0,0 +1,112 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/adc.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>,
+ *         Perry Hung <perry@leaflabs.com>
+ * @brief STM32F1 ADC support.
+ */
+
+#include <libmaple/adc.h>
+#include <libmaple/gpio.h>
+
+/*
+ * Devices
+ */
+
+static adc_dev adc1 = {
+    .regs   = ADC1_BASE,
+    .clk_id = RCC_ADC1,
+};
+/** ADC1 device. */
+const adc_dev *ADC1 = &adc1;
+
+static adc_dev adc2 = {
+    .regs   = ADC2_BASE,
+    .clk_id = RCC_ADC2,
+};
+/** ADC2 device. */
+const adc_dev *ADC2 = &adc2;
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+static adc_dev adc3 = {
+    .regs   = ADC3_BASE,
+    .clk_id = RCC_ADC3,
+};
+/** ADC3 device. */
+const adc_dev *ADC3 = &adc3;
+#endif
+
+/*
+ * STM32F1 routines
+ */
+
+/**
+ * @brief Calibrate an ADC peripheral
+ * @param dev adc device
+ */
+void adc_calibrate(const adc_dev *dev) {
+    __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
+    __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
+
+    *rstcal_bit = 1;
+    while (*rstcal_bit)
+        ;
+
+    *cal_bit = 1;
+    while (*cal_bit)
+        ;
+}
+
+/*
+ * Common routines
+ */
+
+void adc_set_prescaler(adc_prescaler pre) {
+    rcc_set_prescaler(RCC_PRESCALER_ADC, (uint32)pre);
+}
+
+void adc_foreach(void (*fn)(const adc_dev*)) {
+    fn(ADC1);
+    fn(ADC2);
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+    fn(ADC3);
+#endif
+}
+
+void adc_config_gpio(const adc_dev *ignored, gpio_dev *gdev, uint8 bit) {
+    gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG);
+}
+
+void adc_enable_single_swstart(const adc_dev *dev) {
+    adc_init(dev);
+    adc_set_extsel(dev, ADC_SWSTART);
+    adc_set_exttrig(dev, 1);
+    adc_enable(dev);
+    adc_calibrate(dev);
+}

libmaple/bkp.c → libmaple/stm32f1/bkp.c

@@ -25,14 +25,14 @@
  *****************************************************************************/
 
 /**
- * @file bkp.c
- * @brief Backup register support.
+ * @file libmaple/stm32f1/bkp.c
+ * @brief STM32F1 Backup register support.
  */
 
-#include "bkp.h"
-#include "pwr.h"
-#include "rcc.h"
-#include "bitband.h"
+#include <libmaple/bkp.h>
+#include <libmaple/pwr.h>
+#include <libmaple/rcc.h>
+#include <libmaple/bitband.h>
 
 static inline __io uint32* data_register(uint8 reg);
 

libmaple/stm32f1/dma.c

@@ -0,0 +1,412 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Michael Hope.
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/dma.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>;
+ *         Original implementation by Michael Hope
+ * @brief STM32F1 DMA support.
+ */
+
+#include <libmaple/dma.h>
+#include <libmaple/bitband.h>
+
+/* Hack to ensure inlining in dma_irq_handler() */
+#define DMA_GET_HANDLER(dev, tube) (dev->handlers[tube - 1].handler)
+#include "dma_private.h"
+
+/*
+ * Devices
+ */
+
+static dma_dev dma1 = {
+    .regs     = DMA1_BASE,
+    .clk_id   = RCC_DMA1,
+    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH2 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH3 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH4 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH5 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH6 },
+                 { .handler = NULL, .irq_line = NVIC_DMA_CH7 }},
+};
+/** STM32F1 DMA1 device */
+dma_dev *DMA1 = &dma1;
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+static dma_dev dma2 = {
+    .regs     = DMA2_BASE,
+    .clk_id   = RCC_DMA2,
+    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1   },
+                 { .handler = NULL, .irq_line = NVIC_DMA2_CH2   },
+                 { .handler = NULL, .irq_line = NVIC_DMA2_CH3   },
+                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
+                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }}, /* !@#$ */
+};
+/** STM32F1 DMA2 device */
+dma_dev *DMA2 = &dma2;
+#endif
+
+/*
+ * Auxiliary routines
+ */
+
+/* Can channel serve cfg->tube_req_src? */
+static int cfg_req_ok(dma_channel channel, dma_tube_config *cfg) {
+    return (cfg->tube_req_src & 0x7) == channel;
+}
+
+/* Can dev serve cfg->tube_req_src? */
+static int cfg_dev_ok(dma_dev *dev, dma_tube_config *cfg) {
+    return (rcc_clk_id)(cfg->tube_req_src >> 3) == dev->clk_id;
+}
+
+/* Is addr acceptable for use as DMA src/dst? */
+static int cfg_mem_ok(__io void *addr) {
+    enum dma_atype atype = _dma_addr_type(addr);
+    return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER;
+}
+
+/* Is the direction implied by src->dst supported? */
+static int cfg_dir_ok(dma_tube_config *cfg) {
+    /* We can't do peripheral->peripheral transfers. */
+    return ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) ||
+            (_dma_addr_type(cfg->tube_dst) == DMA_ATYPE_MEM));
+}
+
+static int preconfig_check(dma_dev *dev, dma_channel channel,
+                           dma_tube_config *cfg) {
+    if (!cfg_req_ok(channel, cfg)) {
+        return -DMA_TUBE_CFG_EREQ;
+    }
+    if (cfg->tube_nr_xfers > 65535) {
+        return -DMA_TUBE_CFG_ENDATA;
+    }
+    if (!cfg_dev_ok(dev, cfg)) {
+        return -DMA_TUBE_CFG_EDEV;
+    }
+    if (!cfg_mem_ok(cfg->tube_src)) {
+        return -DMA_TUBE_CFG_ESRC;
+    }
+    if (!cfg_mem_ok(cfg->tube_dst)) {
+        return -DMA_TUBE_CFG_EDST;
+    }
+    if (!cfg_dir_ok(cfg)) {
+        return -DMA_TUBE_CFG_EDIR;
+    }
+    return DMA_TUBE_CFG_SUCCESS;
+}
+
+static inline void set_ccr(dma_tube_reg_map *chregs,
+                           dma_xfer_size msize, int minc,
+                           dma_xfer_size psize, int pinc,
+                           uint32 other_flags) {
+    chregs->CCR = ((msize << 10) | (psize << 8) |
+                   (minc ? DMA_CCR_MINC : 0) | (pinc ? DMA_CCR_PINC : 0) |
+                   other_flags);
+}
+
+static inline uint32 cfg_ccr_flags(unsigned tube_flags) {
+    /* DMA_CFG_SRC_INC and DMA_CFG_DST_INC are special */
+    return tube_flags & ~(DMA_CFG_SRC_INC | DMA_CFG_DST_INC);
+}
+
+/* Configure chregs according to cfg, where cfg->tube_dst is peripheral. */
+static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) {
+    /* Check that ->tube_src is memory (if it's anything else, we
+     * shouldn't have been called). */
+    ASSERT(_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM);
+
+    set_ccr(chregs,
+            cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC,
+            cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC,
+            (cfg_ccr_flags(cfg->tube_flags) | DMA_CCR_DIR_FROM_MEM));
+    chregs->CMAR = (uint32)cfg->tube_src;
+    chregs->CPAR = (uint32)cfg->tube_dst;
+    return DMA_TUBE_CFG_SUCCESS;
+}
+
+/* Configure chregs according to cfg, where cfg->tube_dst is memory. */
+static int config_to_mem(dma_tube_reg_map *chregs, dma_tube_config *cfg) {
+    uint32 mem2mem;
+
+    if ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) &&
+        (cfg->tube_flags & DMA_CFG_CIRC)) {
+        /* Can't do mem-to-mem and circular mode */
+        return -DMA_TUBE_CFG_ECFG;
+    }
+
+    mem2mem = (_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM ?
+               DMA_CCR_MEM2MEM : 0);
+    set_ccr(chregs,
+            cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC,
+            cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC,
+            (cfg_ccr_flags(cfg->tube_flags) |
+             DMA_CCR_DIR_FROM_PER |
+             mem2mem));
+    chregs->CNDTR = cfg->tube_nr_xfers;
+    chregs->CMAR = (uint32)cfg->tube_dst;
+    chregs->CPAR = (uint32)cfg->tube_src;
+    return DMA_TUBE_CFG_SUCCESS;
+}
+
+/*
+ * Routines
+ */
+
+int dma_tube_cfg(dma_dev *dev, dma_channel channel, dma_tube_config *cfg) {
+    dma_tube_reg_map *chregs;
+    int ret = preconfig_check(dev, channel, cfg);
+
+    if (ret < 0) {
+        return ret;
+    }
+
+    dma_disable(dev, channel);        /* Must disable before reconfiguring */
+    dma_clear_isr_bits(dev, channel); /* For sanity and consistency
+                                       * with STM32F2. */
+
+    chregs = dma_tube_regs(dev, channel);
+    switch (_dma_addr_type(cfg->tube_dst)) {
+    case DMA_ATYPE_PER:
+        ret = config_to_per(chregs, cfg);
+        break;
+    case DMA_ATYPE_MEM:
+        ret = config_to_mem(chregs, cfg);
+        break;
+    default:
+        /* Can't happen */
+        ASSERT(0);
+        return -DMA_TUBE_CFG_ECFG;
+    }
+    if (ret < 0) {
+        return ret;
+    }
+    chregs->CNDTR = cfg->tube_nr_xfers;
+    return DMA_TUBE_CFG_SUCCESS;
+}
+
+void dma_set_priority(dma_dev *dev,
+                      dma_channel channel,
+                      dma_priority priority) {
+    dma_channel_reg_map *channel_regs;
+    uint32 ccr;
+
+    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
+
+    channel_regs = dma_channel_regs(dev, channel);
+    ccr = channel_regs->CCR;
+    ccr &= ~DMA_CCR_PL;
+    ccr |= (priority << 12);
+    channel_regs->CCR = ccr;
+}
+
+void dma_set_num_transfers(dma_dev *dev,
+                           dma_channel channel,
+                           uint16 num_transfers) {
+    dma_channel_reg_map *channel_regs;
+
+    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
+
+    channel_regs = dma_channel_regs(dev, channel);
+    channel_regs->CNDTR = num_transfers;
+}
+
+void dma_attach_interrupt(dma_dev *dev, dma_channel channel,
+                          void (*handler)(void)) {
+    DMA_GET_HANDLER(dev, channel) = handler;
+    nvic_irq_enable(dev->handlers[channel - 1].irq_line);
+}
+
+void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
+    /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
+    dma_channel_regs(dev, channel)->CCR &= ~0xF;
+    DMA_GET_HANDLER(dev, channel) = NULL;
+}
+
+void dma_enable(dma_dev *dev, dma_channel channel) {
+    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
+    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
+}
+
+void dma_disable(dma_dev *dev, dma_channel channel) {
+    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
+    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
+}
+
+dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
+    /* Grab and clear the ISR bits. */
+    uint8 status_bits = dma_get_isr_bits(dev, channel);
+    dma_clear_isr_bits(dev, channel);
+
+    /* If the channel global interrupt flag is cleared, then
+     * something's very wrong. */
+    ASSERT(status_bits & 0x1);
+    /* If GIF is set, then some other flag should be set, barring
+     * something unexpected (e.g. the user making an unforeseen IFCR
+     * write). */
+    ASSERT(status_bits != 0x1);
+
+    /* ISR flags get set even if the corresponding interrupt enable
+     * bits in the channel's configuration register are cleared, so we
+     * can't use a switch here.
+     *
+     * Don't change the order of these if statements. */
+    if (status_bits & 0x8) {
+        return DMA_TRANSFER_ERROR;
+    } else if (status_bits & 0x2) {
+        return DMA_TRANSFER_COMPLETE;
+    } else if (status_bits & 0x4) {
+        return DMA_TRANSFER_HALF_COMPLETE;
+    }
+
+    /* If we get here, one of our assumptions has been violated, but
+     * the debug level is too low for the above ASSERTs() to have had
+     * any effect. In order to fail fast, mimic the DMA controller's
+     * behavior when an error occurs. */
+    dma_disable(dev, channel);
+    return DMA_TRANSFER_ERROR;
+}
+
+void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
+    dma_channel_reg_map *chan_regs;
+
+    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
+
+    chan_regs = dma_channel_regs(dev, channel);
+    chan_regs->CMAR = (uint32)addr;
+}
+
+void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
+    dma_channel_reg_map *chan_regs;
+
+    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
+
+    chan_regs = dma_channel_regs(dev, channel);
+    chan_regs->CPAR = (uint32)addr;
+}
+
+/**
+ * @brief Deprecated. Use dma_tube_cfg() instead.
+ *
+ * Set up a DMA transfer.
+ *
+ * The channel will be disabled before being reconfigured.  The
+ * transfer will have low priority by default.  You may choose another
+ * priority before the transfer begins using dma_set_priority(), as
+ * well as performing any other configuration you desire.  When the
+ * channel is configured to your liking, enable it using dma_enable().
+ *
+ * @param dev DMA device.
+ * @param channel DMA channel.
+ * @param peripheral_address Base address of peripheral data register
+ *                           involved in the transfer.
+ * @param peripheral_size Peripheral data transfer size.
+ * @param memory_address Base memory address involved in the transfer.
+ * @param memory_size Memory data transfer size.
+ * @param mode Logical OR of dma_mode_flags
+ *
+ * @see dma_tube_cfg()
+ *
+ * @sideeffect Disables the given DMA channel.
+ * @see dma_xfer_size
+ * @see dma_mode_flags
+ * @see dma_set_num_transfers()
+ * @see dma_set_priority()
+ * @see dma_attach_interrupt()
+ * @see dma_enable()
+ */
+__deprecated
+void dma_setup_transfer(dma_dev       *dev,
+                        dma_channel    channel,
+                        __io void     *peripheral_address,
+                        dma_xfer_size  peripheral_size,
+                        __io void     *memory_address,
+                        dma_xfer_size  memory_size,
+                        uint32         mode) {
+    dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
+
+    dma_disable(dev, channel);  /* can't write to CMAR/CPAR otherwise */
+    channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
+    channel_regs->CMAR = (uint32)memory_address;
+    channel_regs->CPAR = (uint32)peripheral_address;
+}
+
+/*
+ * IRQ handlers
+ */
+
+void __irq_dma1_channel1(void) {
+    dma_irq_handler(DMA1, DMA_CH1);
+}
+
+void __irq_dma1_channel2(void) {
+    dma_irq_handler(DMA1, DMA_CH2);
+}
+
+void __irq_dma1_channel3(void) {
+    dma_irq_handler(DMA1, DMA_CH3);
+}
+
+void __irq_dma1_channel4(void) {
+    dma_irq_handler(DMA1, DMA_CH4);
+}
+
+void __irq_dma1_channel5(void) {
+    dma_irq_handler(DMA1, DMA_CH5);
+}
+
+void __irq_dma1_channel6(void) {
+    dma_irq_handler(DMA1, DMA_CH6);
+}
+
+void __irq_dma1_channel7(void) {
+    dma_irq_handler(DMA1, DMA_CH7);
+}
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+void __irq_dma2_channel1(void) {
+    dma_irq_handler(DMA2, DMA_CH1);
+}
+
+void __irq_dma2_channel2(void) {
+    dma_irq_handler(DMA2, DMA_CH2);
+}
+
+void __irq_dma2_channel3(void) {
+    dma_irq_handler(DMA2, DMA_CH3);
+}
+
+void __irq_dma2_channel4_5(void) {
+    if ((DMA2_BASE->CCR4 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF4)) {
+        dma_irq_handler(DMA2, DMA_CH4);
+    }
+    if ((DMA2_BASE->CCR5 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF5)) {
+        dma_irq_handler(DMA2, DMA_CH5);
+    }
+}
+#endif

libmaple/stm32f1/exti.c

@@ -0,0 +1,32 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+#include <libmaple/gpio.h>
+#include "exti_private.h"
+
+void exti_select(exti_num num, exti_cfg port) {
+    exti_do_select(&AFIO_BASE->EXTICR1 + num / 4, num, port);
+}

libmaple/fsmc.c → libmaple/stm32f1/fsmc.c

@@ -1,6 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
+ * Copyright (c) 2012 LeafLabs, LLC.
  * Copyright (c) 2010 Bryan Newbold.
  *
  * Permission is hereby granted, free of charge, to any person
@@ -25,18 +26,19 @@
  *****************************************************************************/
 
 /**
- * @file fsmc.c
- * @brief Flexible static memory controller support.
+ * @file libmaple/stm32f1/fsmc.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>,
+ *         Bryan Newbold <bnewbold@robocracy.org>
+ * @brief STM32F1 FSMC support.
  */
 
-#include "fsmc.h"
-#include "gpio.h"
+#include <libmaple/stm32.h>
 
-#ifdef STM32_HIGH_DENSITY
+#if STM32_HAVE_FSMC /* Don't try building the rest for MCUs without FSMC */
+
+#include <libmaple/fsmc.h>
+#include <libmaple/gpio.h>
 
-/**
- * Configure FSMC GPIOs for use with SRAM.
- */
 void fsmc_sram_init_gpios(void) {
     /* Data lines... */
     gpio_set_mode(GPIOD,  0, GPIO_AF_OUTPUT_PP);
@@ -90,4 +92,4 @@ void fsmc_sram_init_gpios(void) {
     gpio_set_mode(GPIOE,  1, GPIO_AF_OUTPUT_PP);   // NBL1
 }
 
-#endif  /* STM32_HIGH_DENSITY */
+#endif  /* STM32_HAVE_FSMC */

libmaple/stm32f1/gpio.c

@@ -0,0 +1,166 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/gpio.c
+ * @brief STM32F1 GPIO support.
+ */
+
+#include <libmaple/gpio.h>
+#include <libmaple/rcc.h>
+
+/*
+ * GPIO devices
+ */
+
+gpio_dev gpioa = {
+    .regs      = GPIOA_BASE,
+    .clk_id    = RCC_GPIOA,
+    .exti_port = EXTI_PA,
+};
+/** GPIO port A device. */
+gpio_dev* const GPIOA = &gpioa;
+
+gpio_dev gpiob = {
+    .regs      = GPIOB_BASE,
+    .clk_id    = RCC_GPIOB,
+    .exti_port = EXTI_PB,
+};
+/** GPIO port B device. */
+gpio_dev* const GPIOB = &gpiob;
+
+gpio_dev gpioc = {
+    .regs      = GPIOC_BASE,
+    .clk_id    = RCC_GPIOC,
+    .exti_port = EXTI_PC,
+};
+/** GPIO port C device. */
+gpio_dev* const GPIOC = &gpioc;
+
+gpio_dev gpiod = {
+    .regs      = GPIOD_BASE,
+    .clk_id    = RCC_GPIOD,
+    .exti_port = EXTI_PD,
+};
+/** GPIO port D device. */
+gpio_dev* const GPIOD = &gpiod;
+
+#ifdef STM32_HIGH_DENSITY
+gpio_dev gpioe = {
+    .regs      = GPIOE_BASE,
+    .clk_id    = RCC_GPIOE,
+    .exti_port = EXTI_PE,
+};
+/** GPIO port E device. */
+gpio_dev* const GPIOE = &gpioe;
+
+gpio_dev gpiof = {
+    .regs      = GPIOF_BASE,
+    .clk_id    = RCC_GPIOF,
+    .exti_port = EXTI_PF,
+};
+/** GPIO port F device. */
+gpio_dev* const GPIOF = &gpiof;
+
+gpio_dev gpiog = {
+    .regs      = GPIOG_BASE,
+    .clk_id    = RCC_GPIOG,
+    .exti_port = EXTI_PG,
+};
+/** GPIO port G device. */
+gpio_dev* const GPIOG = &gpiog;
+#endif
+
+/*
+ * GPIO routines
+ */
+
+/**
+ * Initialize and reset all available GPIO devices.
+ */
+void gpio_init_all(void) {
+    gpio_init(GPIOA);
+    gpio_init(GPIOB);
+    gpio_init(GPIOC);
+    gpio_init(GPIOD);
+#ifdef STM32_HIGH_DENSITY
+    gpio_init(GPIOE);
+    gpio_init(GPIOF);
+    gpio_init(GPIOG);
+#endif
+}
+
+/**
+ * Set the mode of a GPIO pin.
+ *
+ * @param dev GPIO device.
+ * @param pin Pin on the device whose mode to set, 0--15.
+ * @param mode General purpose or alternate function mode to set the pin to.
+ * @see gpio_pin_mode
+ */
+void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
+    gpio_reg_map *regs = dev->regs;
+    __io uint32 *cr = &regs->CRL + (pin >> 3);
+    uint32 shift = (pin & 0x7) * 4;
+    uint32 tmp = *cr;
+
+    tmp &= ~(0xF << shift);
+    tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift;
+    *cr = tmp;
+
+    if (mode == GPIO_INPUT_PD) {
+        regs->ODR &= ~(1U << pin);
+    } else if (mode == GPIO_INPUT_PU) {
+        regs->ODR |= (1U << pin);
+    }
+}
+
+/*
+ * AFIO
+ */
+
+/**
+ * @brief Initialize the AFIO clock, and reset the AFIO registers.
+ */
+void afio_init(void) {
+    rcc_clk_enable(RCC_AFIO);
+    rcc_reset_dev(RCC_AFIO);
+}
+
+#define AFIO_EXTI_SEL_MASK 0xF
+
+/**
+ * @brief Perform an alternate function remap.
+ * @param remapping Remapping to perform.
+ */
+void afio_remap(afio_remap_peripheral remapping) {
+    if (remapping & AFIO_REMAP_USE_MAPR2) {
+        remapping &= ~AFIO_REMAP_USE_MAPR2;
+        AFIO_BASE->MAPR2 |= remapping;
+    } else {
+        AFIO_BASE->MAPR |= remapping;
+    }
+}

libmaple/stm32f1/i2c.c

@@ -0,0 +1,129 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/i2c.c
+ * @brief STM32F1 I2C support
+ */
+
+#include "i2c_private.h"
+#include <libmaple/i2c.h>
+
+/*
+ * Devices
+ */
+
+static i2c_dev i2c1 = I2C_DEV_OLD(1, &gpiob, 7, 6);
+static i2c_dev i2c2 = I2C_DEV_OLD(2, &gpiob, 11, 10);
+
+/** STM32F1 I2C device 1 */
+i2c_dev* const I2C1 = &i2c1;
+/** STM32F1 I2C device 2 */
+i2c_dev* const I2C2 = &i2c2;
+
+/*
+ * Routines
+ */
+
+static int i2c1_wants_remap(const i2c_dev *dev) {
+    /* Check if we've got I2C1 configured for SDA/SCL remap on PB9/PB8 */
+    return (dev->clk_id == RCC_I2C1) &&
+        (scl_port(dev)->clk_id == RCC_GPIOB) &&
+        (sda_port(dev)->clk_id == RCC_GPIOB) &&
+        (dev->sda_pin == 9) &&
+        (dev->scl_pin == 8);
+}
+
+void i2c_config_gpios(const i2c_dev *dev) {
+    if (i2c1_wants_remap(dev)) {
+        afio_remap(AFIO_REMAP_I2C1);
+    }
+    gpio_set_mode(sda_port(dev), dev->sda_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(scl_port(dev), dev->scl_pin, GPIO_AF_OUTPUT_OD);
+}
+
+void i2c_master_release_bus(const i2c_dev *dev) {
+    gpio_write_bit(scl_port(dev), dev->scl_pin, 1);
+    gpio_write_bit(sda_port(dev), dev->sda_pin, 1);
+    gpio_set_mode(scl_port(dev), dev->scl_pin, GPIO_OUTPUT_OD);
+    gpio_set_mode(sda_port(dev), dev->sda_pin, GPIO_OUTPUT_OD);
+}
+
+/*
+ * IRQ handlers
+ */
+
+void __irq_i2c1_ev(void) {
+   _i2c_irq_handler(I2C1);
+}
+
+void __irq_i2c2_ev(void) {
+   _i2c_irq_handler(I2C2);
+}
+
+void __irq_i2c1_er(void) {
+    _i2c_irq_error_handler(I2C1);
+}
+
+void __irq_i2c2_er(void) {
+    _i2c_irq_error_handler(I2C2);
+}
+
+/*
+ * Internal APIs
+ */
+
+void _i2c_irq_priority_fixup(i2c_dev *dev) {
+    /*
+     * Important STM32 Errata:
+     *
+     * See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8),
+     * Section 2.11.1, 2.11.2.
+     *
+     * 2.11.1:
+     * When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not
+     * managed before the current byte is being transferred, problems may be
+     * encountered such as receiving an extra byte, reading the same data twice
+     * or missing data.
+     *
+     * 2.11.2:
+     * In Master Receiver mode, when closing the communication using
+     * method 2, the content of the last read data can be corrupted.
+     *
+     * If the user software is not able to read the data N-1 before the STOP
+     * condition is generated on the bus, the content of the shift register
+     * (data N) will be corrupted. (data N is shifted 1-bit to the left).
+     *
+     * ----------------------------------------------------------------------
+     *
+     * In order to ensure that events are not missed, the i2c interrupt must
+     * not be preempted. We set the i2c interrupt priority to be the highest
+     * interrupt in the system (priority level 0). All other interrupts have
+     * been initialized to priority level 16. See nvic_init().
+     */
+    nvic_irq_set_priority(dev->ev_nvic_line, 0);
+    nvic_irq_set_priority(dev->er_nvic_line, 0);
+}

libmaple/stm32f1/include/series/adc.h

@@ -0,0 +1,254 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/adc.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>,
+ *         Perry Hung <perry@leaflabs.com>
+ * @brief STM32F1 ADC header.
+ */
+
+#ifndef _LIBMAPLE_STM32F1_ADC_H_
+#define _LIBMAPLE_STM32F1_ADC_H_
+
+#include <libmaple/bitband.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>       /* For the prescalers */
+
+/*
+ * Devices
+ */
+
+extern const struct adc_dev *ADC1;
+extern const struct adc_dev *ADC2;
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+extern const struct adc_dev *ADC3;
+#endif
+
+/*
+ * Register map base pointers
+ */
+
+/** ADC1 register map base pointer. */
+#define ADC1_BASE                       ((struct adc_reg_map*)0x40012400)
+/** ADC2 register map base pointer. */
+#define ADC2_BASE                       ((struct adc_reg_map*)0x40012800)
+/** ADC3 register map base pointer. */
+#define ADC3_BASE                       ((struct adc_reg_map*)0x40013C00)
+
+/*
+ * Register bit definitions
+ */
+
+/* Control register 2 */
+
+#define ADC_CR2_ADON_BIT                0
+#define ADC_CR2_CONT_BIT                1
+#define ADC_CR2_CAL_BIT                 2
+#define ADC_CR2_RSTCAL_BIT              3
+#define ADC_CR2_DMA_BIT                 8
+#define ADC_CR2_ALIGN_BIT               11
+#define ADC_CR2_JEXTTRIG_BIT            15
+#define ADC_CR2_EXTTRIG_BIT             20
+#define ADC_CR2_JSWSTART_BIT            21
+#define ADC_CR2_SWSTART_BIT             22
+#define ADC_CR2_TSEREFE_BIT             23
+
+#define ADC_CR2_ADON                    (1U << ADC_CR2_ADON_BIT)
+#define ADC_CR2_CONT                    (1U << ADC_CR2_CONT_BIT)
+#define ADC_CR2_CAL                     (1U << ADC_CR2_CAL_BIT)
+#define ADC_CR2_RSTCAL                  (1U << ADC_CR2_RSTCAL_BIT)
+#define ADC_CR2_DMA                     (1U << ADC_CR2_DMA_BIT)
+#define ADC_CR2_ALIGN                   (1U << ADC_CR2_ALIGN_BIT)
+#define ADC_CR2_JEXTSEL                 0x7000
+#define ADC_CR2_JEXTTRIG                (1U << ADC_CR2_JEXTTRIG_BIT)
+#define ADC_CR2_EXTSEL                  0xE0000
+#define ADC_CR2_EXTTRIG                 (1U << ADC_CR2_EXTTRIG_BIT)
+#define ADC_CR2_JSWSTART                (1U << ADC_CR2_JSWSTART_BIT)
+#define ADC_CR2_SWSTART                 (1U << ADC_CR2_SWSTART_BIT)
+#define ADC_CR2_TSEREFE                 (1U << ADC_CR2_TSEREFE_BIT)
+
+/*
+ * Other types
+ */
+
+/**
+ * @brief STM32F1 external event selectors for regular group
+ *        conversion.
+ *
+ * Some external events are only available on ADCs 1 and 2, others
+ * only on ADC3, while others are available on all three ADCs.
+ * Additionally, some events are only available on high- and
+ * XL-density STM32F1 MCUs, as they use peripherals only available on
+ * those MCU densities.
+ *
+ * For ease of use, each event selector is given along with the ADCs
+ * it's available on, along with any other availability restrictions.
+ *
+ * @see adc_set_extsel()
+ */
+typedef enum adc_extsel_event {
+    /* TODO: Smarten this up a bit, as follows.
+     *
+     * The EXTSEL bits on F1 are a little brain-damaged in that the
+     * TIM8 TRGO event has different bits depending on whether you're
+     * using ADC1/2 or ADC3.  We route around this by declaring two
+     * enumerators, ADC_EXT_EV_ADC12_TIM8_TRGO and
+     * ADC_EXT_EV_ADC3_TIM8_TRGO.
+     *
+     * The right thing to do is to provide a single
+     * ADC_EXT_EV_TIM8_TRGO enumerator and override adc_set_extsel on
+     * STM32F1 to handle this situation correctly. We can do that
+     * later, though, and change the per-ADC enumerator values to
+     * ADC_EXT_EV_TIM8_TRGO to preserve compatibility. */
+
+    /* ADC1 and ADC2 only: */
+    ADC_EXT_EV_TIM1_CC1  = 0x00000, /**< ADC1, ADC2: Timer 1 CC1 event */
+    ADC_EXT_EV_TIM1_CC2  = 0x20000, /**< ADC1, ADC2: Timer 1 CC2 event */
+    ADC_EXT_EV_TIM2_CC2  = 0x60000, /**< ADC1, ADC2: Timer 2 CC2 event */
+    ADC_EXT_EV_TIM3_TRGO = 0x80000, /**< ADC1, ADC2: Timer 3 TRGO event */
+    ADC_EXT_EV_TIM4_CC4  = 0xA0000, /**< ADC1, ADC2: Timer 4 CC4 event */
+    ADC_EXT_EV_EXTI11    = 0xC0000, /**< ADC1, ADC2: EXTI11 event */
+
+    /* Common: */
+    ADC_EXT_EV_TIM1_CC3  = 0x40000, /**< ADC1, ADC2, ADC3: Timer 1 CC3 event */
+    ADC_EXT_EV_SWSTART   = 0xE0000, /**< ADC1, ADC2, ADC3: Software start */
+
+    /* HD only: */
+    ADC_EXT_EV_TIM3_CC1  = 0x00000, /**<
+                                     * ADC3: Timer 3 CC1 event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_TIM2_CC3  = 0x20000, /**<
+                                     * ADC3: Timer 2 CC3 event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_TIM8_CC1  = 0x60000, /**<
+                                     * ADC3: Timer 8 CC1 event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_ADC3_TIM8_TRGO = 0x80000, /**<
+                                     * ADC3: Timer 8 TRGO event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_TIM5_CC1  = 0xA0000, /**<
+                                     * ADC3: Timer 5 CC1 event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_ADC12_TIM8_TRGO = 0xC0000, /**<
+                                     * ADC1, ADC2: Timer 8 TRGO event
+                                     * Availability: high- and XL-density. */
+    ADC_EXT_EV_TIM5_CC3  = 0xC0000, /**<
+                                     * ADC3: Timer 5 CC3 event
+                                     * Availability: high- and XL-density. */
+} adc_extsel_event;
+
+/* We'll keep these old adc_extsel_event enumerators around for a
+ * while, for backwards compatibility: */
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */
+#define ADC_ADC12_TIM1_CC1  ADC_EXT_EV_TIM1_CC1
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */
+#define ADC_ADC12_TIM1_CC2  ADC_EXT_EV_TIM1_CC2
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */
+#define ADC_ADC12_TIM1_CC3  ADC_EXT_EV_TIM1_CC3
+/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */
+#define ADC_ADC12_TIM2_CC2  ADC_EXT_EV_TIM2_CC2
+/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */
+#define ADC_ADC12_TIM3_TRGO ADC_EXT_EV_TIM3_TRGO
+/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */
+#define ADC_ADC12_TIM4_CC4  ADC_EXT_EV_TIM4_CC4
+/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */
+#define ADC_ADC12_EXTI11    ADC_EXT_EV_EXTI11
+/** Deprecated. Use ADC_EXT_EV_ADC12_TIM8_TRGO instead. */
+#define ADC_ADC12_TIM8_TRGO ADC_EXT_EV_ADC12_TIM8_TRGO
+/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */
+#define ADC_ADC12_SWSTART   ADC_EXT_EV_SWSTART
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */
+#define ADC_ADC3_TIM3_CC1   ADC_EXT_EV_TIM1_CC1
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */
+#define ADC_ADC3_TIM2_CC3   ADC_EXT_EV_TIM1_CC2
+/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */
+#define ADC_ADC3_TIM1_CC3   ADC_EXT_EV_TIM1_CC3
+/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */
+#define ADC_ADC3_TIM8_CC1   ADC_EXT_EV_TIM2_CC2
+/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */
+#define ADC_ADC3_TIM8_TRGO  ADC_EXT_EV_TIM3_TRGO
+/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */
+#define ADC_ADC3_TIM5_CC1   ADC_EXT_EV_TIM4_CC4
+/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */
+#define ADC_ADC3_TIM5_CC3   ADC_EXT_EV_EXTI11
+/** Deprecated. Use ADC_EXT_EV_TIM8_TRGO instead. */
+#define ADC_ADC3_SWSTART    ADC_EXT_EV_TIM8_TRGO
+/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */
+#define ADC_SWSTART         ADC_EXT_EV_SWSTART
+
+/**
+ * @brief STM32F1 sample times, in ADC clock cycles.
+ *
+ * These control the amount of time spent sampling the input voltage.
+ *
+ * IMPORTANT: maximum external impedance must be below 0.4kOhms for
+ * 1.5 cycle sampling time. At 55.5 cycles/sample, the external input
+ * impedance must be at most 50kOhms. See your device's datasheet for
+ * more information.
+ */
+typedef enum adc_smp_rate {
+    ADC_SMPR_1_5,               /**< 1.5 ADC cycles */
+    ADC_SMPR_7_5,               /**< 7.5 ADC cycles */
+    ADC_SMPR_13_5,              /**< 13.5 ADC cycles */
+    ADC_SMPR_28_5,              /**< 28.5 ADC cycles */
+    ADC_SMPR_41_5,              /**< 41.5 ADC cycles */
+    ADC_SMPR_55_5,              /**< 55.5 ADC cycles */
+    ADC_SMPR_71_5,              /**< 71.5 ADC cycles */
+    ADC_SMPR_239_5,             /**< 239.5 ADC cycles */
+} adc_smp_rate;
+
+/**
+ * @brief STM32F1 ADC prescalers, as divisors of PCLK2.
+ */
+typedef enum adc_prescaler {
+    ADC_PRE_PCLK2_DIV_2 = RCC_ADCPRE_PCLK_DIV_2, /** PCLK2 divided by 2 */
+    ADC_PRE_PCLK2_DIV_4 = RCC_ADCPRE_PCLK_DIV_4, /** PCLK2 divided by 4 */
+    ADC_PRE_PCLK2_DIV_6 = RCC_ADCPRE_PCLK_DIV_6, /** PCLK2 divided by 6 */
+    ADC_PRE_PCLK2_DIV_8 = RCC_ADCPRE_PCLK_DIV_8, /** PCLK2 divided by 8 */
+} adc_prescaler;
+
+/*
+ * Routines
+ */
+
+void adc_calibrate(const adc_dev *dev);
+
+/**
+ * @brief Set external trigger conversion mode event for regular channels
+ *
+ * Availability: STM32F1.
+ *
+ * @param dev    ADC device
+ * @param enable If 1, conversion on external events is enabled; if 0,
+ *               disabled.
+ */
+static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
+    *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable;
+}
+
+#endif

libmaple/stm32f1/include/series/dac.h

@@ -0,0 +1,71 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/dac.h
+ * @brief STM32F1 DAC support
+ */
+
+#ifndef _LIBMAPLE_STM32F1_DAC_H_
+#define _LIBMAPLE_STM32F1_DAC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+/** STM32F1 DAC register map type. */
+typedef struct dac_reg_map {
+    __io uint32 CR;      /**< Control register */
+    __io uint32 SWTRIGR; /**< Software trigger register */
+    __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R1;  /**< Channel 1 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R2;  /**< Channel 2 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8RD;  /**< Dual DAC 8-bit right-aligned data holding
+                              register */
+    __io uint32 DOR1;    /**< Channel 1 data output register */
+    __io uint32 DOR2;    /**< Channel 2 data output register */
+} dac_reg_map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libmaple/stm32f1/include/series/dma.h

@@ -0,0 +1,565 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Michael Hope.
+ * Copyright (c) 2012 LeafLabs, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/dma.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>;
+ *         Original implementation by Michael Hope
+ * @brief STM32F1 DMA series header.
+ */
+
+/*
+ * See /notes/dma-stm32f1.txt for more information.
+ */
+
+#ifndef _LIBMAPLE_STM32F1_DMA_H_
+#define _LIBMAPLE_STM32F1_DMA_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/dma_common.h>
+
+/*
+ * Register maps and base pointers
+ */
+
+/**
+ * @brief STM32F1 DMA register map type.
+ *
+ * Note that DMA controller 2 (register map base pointer DMA2_BASE)
+ * only supports channels 1--5.
+ */
+typedef struct dma_reg_map {
+    __io uint32 ISR;            /**< Interrupt status register */
+    __io uint32 IFCR;           /**< Interrupt flag clear register */
+    __io uint32 CCR1;           /**< Channel 1 configuration register */
+    __io uint32 CNDTR1;         /**< Channel 1 number of data register */
+    __io uint32 CPAR1;          /**< Channel 1 peripheral address register */
+    __io uint32 CMAR1;          /**< Channel 1 memory address register */
+    const uint32 RESERVED1;     /**< Reserved. */
+    __io uint32 CCR2;           /**< Channel 2 configuration register */
+    __io uint32 CNDTR2;         /**< Channel 2 number of data register */
+    __io uint32 CPAR2;          /**< Channel 2 peripheral address register */
+    __io uint32 CMAR2;          /**< Channel 2 memory address register */
+    const uint32 RESERVED2;     /**< Reserved. */
+    __io uint32 CCR3;           /**< Channel 3 configuration register */
+    __io uint32 CNDTR3;         /**< Channel 3 number of data register */
+    __io uint32 CPAR3;          /**< Channel 3 peripheral address register */
+    __io uint32 CMAR3;          /**< Channel 3 memory address register */
+    const uint32 RESERVED3;     /**< Reserved. */
+    __io uint32 CCR4;           /**< Channel 4 configuration register */
+    __io uint32 CNDTR4;         /**< Channel 4 number of data register */
+    __io uint32 CPAR4;          /**< Channel 4 peripheral address register */
+    __io uint32 CMAR4;          /**< Channel 4 memory address register */
+    const uint32 RESERVED4;     /**< Reserved. */
+    __io uint32 CCR5;           /**< Channel 5 configuration register */
+    __io uint32 CNDTR5;         /**< Channel 5 number of data register */
+    __io uint32 CPAR5;          /**< Channel 5 peripheral address register */
+    __io uint32 CMAR5;          /**< Channel 5 memory address register */
+    const uint32 RESERVED5;     /**< Reserved. */
+    __io uint32 CCR6;           /**< Channel 6 configuration register */
+    __io uint32 CNDTR6;         /**< Channel 6 number of data register */
+    __io uint32 CPAR6;          /**< Channel 6 peripheral address register */
+    __io uint32 CMAR6;          /**< Channel 6 memory address register */
+    const uint32 RESERVED6;     /**< Reserved. */
+    __io uint32 CCR7;           /**< Channel 7 configuration register */
+    __io uint32 CNDTR7;         /**< Channel 7 number of data register */
+    __io uint32 CPAR7;          /**< Channel 7 peripheral address register */
+    __io uint32 CMAR7;          /**< Channel 7 memory address register */
+    const uint32 RESERVED7;     /**< Reserved. */
+} dma_reg_map;
+
+/** DMA controller 1 register map base pointer */
+#define DMA1_BASE                       ((struct dma_reg_map*)0x40020000)
+/** DMA controller 2 register map base pointer */
+#define DMA2_BASE                       ((struct dma_reg_map*)0x40020400)
+
+/**
+ * @brief STM32F1 DMA channel (i.e. tube) register map type.
+ * Provides access to an individual channel's registers.
+ * @see dma_tube_regs()
+ */
+typedef struct dma_tube_reg_map {
+    __io uint32 CCR;           /**< Channel configuration register */
+    __io uint32 CNDTR;         /**< Channel number of data register */
+    __io uint32 CPAR;          /**< Channel peripheral address register */
+    __io uint32 CMAR;          /**< Channel memory address register */
+} dma_tube_reg_map;
+
+/** DMA1 channel 1 register map base pointer */
+#define DMA1CH1_BASE                ((struct dma_tube_reg_map*)0x40020008)
+/** DMA1 channel 2 register map base pointer */
+#define DMA1CH2_BASE                ((struct dma_tube_reg_map*)0x4002001C)
+/** DMA1 channel 3 register map base pointer */
+#define DMA1CH3_BASE                ((struct dma_tube_reg_map*)0x40020030)
+/** DMA1 channel 4 register map base pointer */
+#define DMA1CH4_BASE                ((struct dma_tube_reg_map*)0x40020044)
+/** DMA1 channel 5 register map base pointer */
+#define DMA1CH5_BASE                ((struct dma_tube_reg_map*)0x40020058)
+/** DMA1 channel 6 register map base pointer */
+#define DMA1CH6_BASE                ((struct dma_tube_reg_map*)0x4002006C)
+/** DMA1 channel 7 register map base pointer */
+#define DMA1CH7_BASE                ((struct dma_tube_reg_map*)0x40020080)
+
+/** DMA2 channel 1 register map base pointer */
+#define DMA2CH1_BASE                ((struct dma_tube_reg_map*)0x40020408)
+/** DMA2 channel 2 register map base pointer */
+#define DMA2CH2_BASE                ((struct dma_tube_reg_map*)0x4002041C)
+/** DMA2 channel 3 register map base pointer */
+#define DMA2CH3_BASE                ((struct dma_tube_reg_map*)0x40020430)
+/** DMA2 channel 4 register map base pointer */
+#define DMA2CH4_BASE                ((struct dma_tube_reg_map*)0x40020444)
+/** DMA2 channel 5 register map base pointer */
+#define DMA2CH5_BASE                ((struct dma_tube_reg_map*)0x40020458)
+
+/*
+ * Register bit definitions
+ */
+
+/* Interrupt status register */
+
+#define DMA_ISR_TEIF7_BIT               27
+#define DMA_ISR_HTIF7_BIT               26
+#define DMA_ISR_TCIF7_BIT               25
+#define DMA_ISR_GIF7_BIT                24
+#define DMA_ISR_TEIF6_BIT               23
+#define DMA_ISR_HTIF6_BIT               22
+#define DMA_ISR_TCIF6_BIT               21
+#define DMA_ISR_GIF6_BIT                20
+#define DMA_ISR_TEIF5_BIT               19
+#define DMA_ISR_HTIF5_BIT               18
+#define DMA_ISR_TCIF5_BIT               17
+#define DMA_ISR_GIF5_BIT                16
+#define DMA_ISR_TEIF4_BIT               15
+#define DMA_ISR_HTIF4_BIT               14
+#define DMA_ISR_TCIF4_BIT               13
+#define DMA_ISR_GIF4_BIT                12
+#define DMA_ISR_TEIF3_BIT               11
+#define DMA_ISR_HTIF3_BIT               10
+#define DMA_ISR_TCIF3_BIT               9
+#define DMA_ISR_GIF3_BIT                8
+#define DMA_ISR_TEIF2_BIT               7
+#define DMA_ISR_HTIF2_BIT               6
+#define DMA_ISR_TCIF2_BIT               5
+#define DMA_ISR_GIF2_BIT                4
+#define DMA_ISR_TEIF1_BIT               3
+#define DMA_ISR_HTIF1_BIT               2
+#define DMA_ISR_TCIF1_BIT               1
+#define DMA_ISR_GIF1_BIT                0
+
+#define DMA_ISR_TEIF7                   (1U << DMA_ISR_TEIF7_BIT)
+#define DMA_ISR_HTIF7                   (1U << DMA_ISR_HTIF7_BIT)
+#define DMA_ISR_TCIF7                   (1U << DMA_ISR_TCIF7_BIT)
+#define DMA_ISR_GIF7                    (1U << DMA_ISR_GIF7_BIT)
+#define DMA_ISR_TEIF6                   (1U << DMA_ISR_TEIF6_BIT)
+#define DMA_ISR_HTIF6                   (1U << DMA_ISR_HTIF6_BIT)
+#define DMA_ISR_TCIF6                   (1U << DMA_ISR_TCIF6_BIT)
+#define DMA_ISR_GIF6                    (1U << DMA_ISR_GIF6_BIT)
+#define DMA_ISR_TEIF5                   (1U << DMA_ISR_TEIF5_BIT)
+#define DMA_ISR_HTIF5                   (1U << DMA_ISR_HTIF5_BIT)
+#define DMA_ISR_TCIF5                   (1U << DMA_ISR_TCIF5_BIT)
+#define DMA_ISR_GIF5                    (1U << DMA_ISR_GIF5_BIT)
+#define DMA_ISR_TEIF4                   (1U << DMA_ISR_TEIF4_BIT)
+#define DMA_ISR_HTIF4                   (1U << DMA_ISR_HTIF4_BIT)
+#define DMA_ISR_TCIF4                   (1U << DMA_ISR_TCIF4_BIT)
+#define DMA_ISR_GIF4                    (1U << DMA_ISR_GIF4_BIT)
+#define DMA_ISR_TEIF3                   (1U << DMA_ISR_TEIF3_BIT)
+#define DMA_ISR_HTIF3                   (1U << DMA_ISR_HTIF3_BIT)
+#define DMA_ISR_TCIF3                   (1U << DMA_ISR_TCIF3_BIT)
+#define DMA_ISR_GIF3                    (1U << DMA_ISR_GIF3_BIT)
+#define DMA_ISR_TEIF2                   (1U << DMA_ISR_TEIF2_BIT)
+#define DMA_ISR_HTIF2                   (1U << DMA_ISR_HTIF2_BIT)
+#define DMA_ISR_TCIF2                   (1U << DMA_ISR_TCIF2_BIT)
+#define DMA_ISR_GIF2                    (1U << DMA_ISR_GIF2_BIT)
+#define DMA_ISR_TEIF1                   (1U << DMA_ISR_TEIF1_BIT)
+#define DMA_ISR_HTIF1                   (1U << DMA_ISR_HTIF1_BIT)
+#define DMA_ISR_TCIF1                   (1U << DMA_ISR_TCIF1_BIT)
+#define DMA_ISR_GIF1                    (1U << DMA_ISR_GIF1_BIT)
+
+/* Interrupt flag clear register */
+
+#define DMA_IFCR_CTEIF7_BIT             27
+#define DMA_IFCR_CHTIF7_BIT             26
+#define DMA_IFCR_CTCIF7_BIT             25
+#define DMA_IFCR_CGIF7_BIT              24
+#define DMA_IFCR_CTEIF6_BIT             23
+#define DMA_IFCR_CHTIF6_BIT             22
+#define DMA_IFCR_CTCIF6_BIT             21
+#define DMA_IFCR_CGIF6_BIT              20
+#define DMA_IFCR_CTEIF5_BIT             19
+#define DMA_IFCR_CHTIF5_BIT             18
+#define DMA_IFCR_CTCIF5_BIT             17
+#define DMA_IFCR_CGIF5_BIT              16
+#define DMA_IFCR_CTEIF4_BIT             15
+#define DMA_IFCR_CHTIF4_BIT             14
+#define DMA_IFCR_CTCIF4_BIT             13
+#define DMA_IFCR_CGIF4_BIT              12
+#define DMA_IFCR_CTEIF3_BIT             11
+#define DMA_IFCR_CHTIF3_BIT             10
+#define DMA_IFCR_CTCIF3_BIT             9
+#define DMA_IFCR_CGIF3_BIT              8
+#define DMA_IFCR_CTEIF2_BIT             7
+#define DMA_IFCR_CHTIF2_BIT             6
+#define DMA_IFCR_CTCIF2_BIT             5
+#define DMA_IFCR_CGIF2_BIT              4
+#define DMA_IFCR_CTEIF1_BIT             3
+#define DMA_IFCR_CHTIF1_BIT             2
+#define DMA_IFCR_CTCIF1_BIT             1
+#define DMA_IFCR_CGIF1_BIT              0
+
+#define DMA_IFCR_CTEIF7                 (1U << DMA_IFCR_CTEIF7_BIT)
+#define DMA_IFCR_CHTIF7                 (1U << DMA_IFCR_CHTIF7_BIT)
+#define DMA_IFCR_CTCIF7                 (1U << DMA_IFCR_CTCIF7_BIT)
+#define DMA_IFCR_CGIF7                  (1U << DMA_IFCR_CGIF7_BIT)
+#define DMA_IFCR_CTEIF6                 (1U << DMA_IFCR_CTEIF6_BIT)
+#define DMA_IFCR_CHTIF6                 (1U << DMA_IFCR_CHTIF6_BIT)
+#define DMA_IFCR_CTCIF6                 (1U << DMA_IFCR_CTCIF6_BIT)
+#define DMA_IFCR_CGIF6                  (1U << DMA_IFCR_CGIF6_BIT)
+#define DMA_IFCR_CTEIF5                 (1U << DMA_IFCR_CTEIF5_BIT)
+#define DMA_IFCR_CHTIF5                 (1U << DMA_IFCR_CHTIF5_BIT)
+#define DMA_IFCR_CTCIF5                 (1U << DMA_IFCR_CTCIF5_BIT)
+#define DMA_IFCR_CGIF5                  (1U << DMA_IFCR_CGIF5_BIT)
+#define DMA_IFCR_CTEIF4                 (1U << DMA_IFCR_CTEIF4_BIT)
+#define DMA_IFCR_CHTIF4                 (1U << DMA_IFCR_CHTIF4_BIT)
+#define DMA_IFCR_CTCIF4                 (1U << DMA_IFCR_CTCIF4_BIT)
+#define DMA_IFCR_CGIF4                  (1U << DMA_IFCR_CGIF4_BIT)
+#define DMA_IFCR_CTEIF3                 (1U << DMA_IFCR_CTEIF3_BIT)
+#define DMA_IFCR_CHTIF3                 (1U << DMA_IFCR_CHTIF3_BIT)
+#define DMA_IFCR_CTCIF3                 (1U << DMA_IFCR_CTCIF3_BIT)
+#define DMA_IFCR_CGIF3                  (1U << DMA_IFCR_CGIF3_BIT)
+#define DMA_IFCR_CTEIF2                 (1U << DMA_IFCR_CTEIF2_BIT)
+#define DMA_IFCR_CHTIF2                 (1U << DMA_IFCR_CHTIF2_BIT)
+#define DMA_IFCR_CTCIF2                 (1U << DMA_IFCR_CTCIF2_BIT)
+#define DMA_IFCR_CGIF2                  (1U << DMA_IFCR_CGIF2_BIT)
+#define DMA_IFCR_CTEIF1                 (1U << DMA_IFCR_CTEIF1_BIT)
+#define DMA_IFCR_CHTIF1                 (1U << DMA_IFCR_CHTIF1_BIT)
+#define DMA_IFCR_CTCIF1                 (1U << DMA_IFCR_CTCIF1_BIT)
+#define DMA_IFCR_CGIF1                  (1U << DMA_IFCR_CGIF1_BIT)
+
+/* Channel configuration register */
+
+#define DMA_CCR_MEM2MEM_BIT             14
+#define DMA_CCR_MINC_BIT                7
+#define DMA_CCR_PINC_BIT                6
+#define DMA_CCR_CIRC_BIT                5
+#define DMA_CCR_DIR_BIT                 4
+#define DMA_CCR_TEIE_BIT                3
+#define DMA_CCR_HTIE_BIT                2
+#define DMA_CCR_TCIE_BIT                1
+#define DMA_CCR_EN_BIT                  0
+
+#define DMA_CCR_MEM2MEM                 (1U << DMA_CCR_MEM2MEM_BIT)
+#define DMA_CCR_PL                      (0x3 << 12)
+#define DMA_CCR_PL_LOW                  (0x0 << 12)
+#define DMA_CCR_PL_MEDIUM               (0x1 << 12)
+#define DMA_CCR_PL_HIGH                 (0x2 << 12)
+#define DMA_CCR_PL_VERY_HIGH            (0x3 << 12)
+#define DMA_CCR_MSIZE                   (0x3 << 10)
+#define DMA_CCR_MSIZE_8BITS             (0x0 << 10)
+#define DMA_CCR_MSIZE_16BITS            (0x1 << 10)
+#define DMA_CCR_MSIZE_32BITS            (0x2 << 10)
+#define DMA_CCR_PSIZE                   (0x3 << 8)
+#define DMA_CCR_PSIZE_8BITS             (0x0 << 8)
+#define DMA_CCR_PSIZE_16BITS            (0x1 << 8)
+#define DMA_CCR_PSIZE_32BITS            (0x2 << 8)
+#define DMA_CCR_MINC                    (1U << DMA_CCR_MINC_BIT)
+#define DMA_CCR_PINC                    (1U << DMA_CCR_PINC_BIT)
+#define DMA_CCR_CIRC                    (1U << DMA_CCR_CIRC_BIT)
+#define DMA_CCR_DIR                     (1U << DMA_CCR_DIR_BIT)
+#define DMA_CCR_DIR_FROM_PER            (0U << DMA_CCR_DIR_BIT)
+#define DMA_CCR_DIR_FROM_MEM            (1U << DMA_CCR_DIR_BIT)
+#define DMA_CCR_TEIE                    (1U << DMA_CCR_TEIE_BIT)
+#define DMA_CCR_HTIE                    (1U << DMA_CCR_HTIE_BIT)
+#define DMA_CCR_TCIE                    (1U << DMA_CCR_TCIE_BIT)
+#define DMA_CCR_EN                      (1U << DMA_CCR_EN_BIT)
+
+/*
+ * Devices
+ */
+
+extern dma_dev *DMA1;
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+extern dma_dev *DMA2;
+#endif
+
+/*
+ * Other types needed by, or useful for, <libmaple/dma.h>.
+ */
+
+/**
+ * @brief STM32F1 dma_tube.
+ * On STM32F1, DMA tubes are just channels.
+ */
+#define dma_tube dma_channel
+
+/**
+ * @brief On STM32F1, dma_channel_reg_map is an alias for dma_tube_reg_map.
+ * This is for backwards compatibility. */
+#define dma_channel_reg_map dma_tube_reg_map
+
+/**
+ * @brief STM32F1 configuration flags for dma_tube_config
+ * @see struct dma_tube_config
+ */
+typedef enum dma_cfg_flags {
+    /**
+     * Source address increment mode
+     *
+     * If this flag is set, the source address is incremented (by the
+     * source size) after each DMA transfer.
+     */
+    DMA_CFG_SRC_INC = 1U << 31,
+
+    /**
+     * Destination address increment mode
+     *
+     * If this flag is set, the destination address is incremented (by
+     * the destination size) after each DMA transfer.
+     */
+    DMA_CFG_DST_INC = 1U << 30,
+
+    /**
+     * Circular mode
+     *
+     * This mode is not available for memory-to-memory transfers.
+     */
+    DMA_CFG_CIRC = DMA_CCR_CIRC,
+
+    /** Transfer complete interrupt enable */
+    DMA_CFG_CMPLT_IE      = DMA_CCR_TCIE,
+    /** Transfer half-complete interrupt enable  */
+    DMA_CFG_HALF_CMPLT_IE = DMA_CCR_HTIE,
+    /** Transfer error interrupt enable */
+    DMA_CFG_ERR_IE        = DMA_CCR_TEIE,
+} dma_cfg_flags;
+
+/**
+ * @brief STM32F1 DMA request sources.
+ *
+ * IMPORTANT:
+ *
+ * 1. On STM32F1, each dma_request_src can only be used by a
+ * particular tube on a particular DMA controller. For example,
+ * DMA_REQ_SRC_ADC1 belongs to DMA1, tube 1. DMA2 cannot serve
+ * requests from ADC1, nor can DMA1 tube 2, etc. If you try to use a
+ * request source with the wrong DMA controller or tube on STM32F1,
+ * dma_tube_cfg() will fail.
+ *
+ * 2. In general, a DMA tube can only serve a single request source at
+ * a time, and on STM32F1, Terrible Super-Bad Things will happen if
+ * two request sources are active for a single tube.
+ *
+ * To make all this easier to sort out, these dma_request_src
+ * enumerators are grouped by DMA controller and tube.
+ *
+ * @see struct dma_tube_config
+ * @see dma_tube_cfg()
+ */
+typedef enum dma_request_src {
+    /* Each request source encodes the DMA controller and channel it
+     * belongs to, for error checking in dma_tube_cfg(). */
+
+    /* DMA1 request sources */
+
+    /**@{*/
+    /** (DMA1, tube 1) */
+    DMA_REQ_SRC_ADC1      = (RCC_DMA1 << 3) | 1,
+    DMA_REQ_SRC_TIM2_CH3  = (RCC_DMA1 << 3) | 1,
+    DMA_REQ_SRC_TIM4_CH1  = (RCC_DMA1 << 3) | 1,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA1, tube 2)*/
+    DMA_REQ_SRC_SPI1_RX   = (RCC_DMA1 << 3) | 2,
+    DMA_REQ_SRC_USART3_TX = (RCC_DMA1 << 3) | 2,
+    DMA_REQ_SRC_TIM1_CH1  = (RCC_DMA1 << 3) | 2,
+    DMA_REQ_SRC_TIM2_UP   = (RCC_DMA1 << 3) | 2,
+    DMA_REQ_SRC_TIM3_CH3  = (RCC_DMA1 << 3) | 2,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA1, tube 3)*/
+    DMA_REQ_SRC_SPI1_TX   = (RCC_DMA1 << 3) | 3,
+    DMA_REQ_SRC_USART3_RX = (RCC_DMA1 << 3) | 3,
+    DMA_REQ_SRC_TIM1_CH2  = (RCC_DMA1 << 3) | 3,
+    DMA_REQ_SRC_TIM3_CH4  = (RCC_DMA1 << 3) | 3,
+    DMA_REQ_SRC_TIM3_UP   = (RCC_DMA1 << 3) | 3,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA1, tube 4)*/
+    DMA_REQ_SRC_SPI2_RX   = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_I2S2_RX   = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_USART1_TX = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_I2C2_TX   = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_TIM1_CH4  = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_TIM1_TRIG = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_TIM1_COM  = (RCC_DMA1 << 3) | 4,
+    DMA_REQ_SRC_TIM4_CH2  = (RCC_DMA1 << 3) | 4,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA1, tube 5)*/
+    DMA_REQ_SRC_SPI2_TX   = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_I2S2_TX   = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_USART1_RX = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_I2C2_RX   = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_TIM1_UP   = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_TIM2_CH1  = (RCC_DMA1 << 3) | 5,
+    DMA_REQ_SRC_TIM4_CH3  = (RCC_DMA1 << 3) | 5,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA1, tube 6)*/
+    DMA_REQ_SRC_USART2_RX = (RCC_DMA1 << 3) | 6,
+    DMA_REQ_SRC_I2C1_TX   = (RCC_DMA1 << 3) | 6,
+    DMA_REQ_SRC_TIM1_CH3  = (RCC_DMA1 << 3) | 6,
+    DMA_REQ_SRC_TIM3_CH1  = (RCC_DMA1 << 3) | 6,
+    DMA_REQ_SRC_TIM3_TRIG = (RCC_DMA1 << 3) | 6,
+    /**@}*/
+
+    /**@{*/
+    /* Tube 7 */
+    DMA_REQ_SRC_USART2_TX = (RCC_DMA1 << 3) | 7,
+    DMA_REQ_SRC_I2C1_RX   = (RCC_DMA1 << 3) | 7,
+    DMA_REQ_SRC_TIM2_CH2  = (RCC_DMA1 << 3) | 7,
+    DMA_REQ_SRC_TIM2_CH4  = (RCC_DMA1 << 3) | 7,
+    DMA_REQ_SRC_TIM4_UP   = (RCC_DMA1 << 3) | 7,
+    /**@}*/
+
+    /* DMA2 request sources */
+
+    /**@{*/
+    /** (DMA2, tube 1)*/
+    DMA_REQ_SRC_SPI3_RX   = (RCC_DMA2 << 3) | 1,
+    DMA_REQ_SRC_I2S3_RX   = (RCC_DMA2 << 3) | 1,
+    DMA_REQ_SRC_TIM5_CH4  = (RCC_DMA2 << 3) | 1,
+    DMA_REQ_SRC_TIM5_TRIG = (RCC_DMA2 << 3) | 1,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA2, tube 2)*/
+    DMA_REQ_SRC_SPI3_TX   = (RCC_DMA2 << 3) | 2,
+    DMA_REQ_SRC_I2S3_TX   = (RCC_DMA2 << 3) | 2,
+    DMA_REQ_SRC_TIM5_CH3  = (RCC_DMA2 << 3) | 2,
+    DMA_REQ_SRC_TIM5_UP   = (RCC_DMA2 << 3) | 2,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA2, tube 3)*/
+    DMA_REQ_SRC_UART4_RX  = (RCC_DMA2 << 3) | 3,
+    DMA_REQ_SRC_TIM6_UP   = (RCC_DMA2 << 3) | 3,
+    DMA_REQ_SRC_DAC_CH1   = (RCC_DMA2 << 3) | 3,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA2, tube 4)*/
+    DMA_REQ_SRC_SDIO      = (RCC_DMA2 << 3) | 4,
+    DMA_REQ_SRC_TIM5_CH2  = (RCC_DMA2 << 3) | 4,
+    /**@}*/
+
+    /**@{*/
+    /** (DMA2, tube 5)*/
+    DMA_REQ_SRC_ADC3      = (RCC_DMA2 << 3) | 5,
+    DMA_REQ_SRC_UART4_TX  = (RCC_DMA2 << 3) | 5,
+    DMA_REQ_SRC_TIM5_CH1  = (RCC_DMA2 << 3) | 5,
+    /**@}*/
+} dma_request_src;
+
+/*
+ * Convenience routines.
+ */
+
+/**
+ * @brief On STM32F1, dma_is_channel_enabled() is an alias for
+ *        dma_is_enabled().
+ * This is for backwards compatibility.
+ */
+#define dma_is_channel_enabled dma_is_enabled
+
+#define DMA_CHANNEL_NREGS 5     /* accounts for reserved word */
+static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube) {
+    __io uint32 *ccr1 = &dev->regs->CCR1;
+    return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (tube - 1));
+}
+
+/**
+ * @brief On STM32F1, dma_channel_regs() is an alias for dma_tube_regs().
+ * This is for backwards compatibility. */
+#define dma_channel_regs(dev, ch) dma_tube_regs(dev, ch)
+
+static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) {
+    return (uint8)(dma_tube_regs(dev, tube)->CCR & DMA_CCR_EN);
+}
+
+static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) {
+    uint8 shift = (tube - 1) * 4;
+    return (dev->regs->ISR >> shift) & 0xF;
+}
+
+static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) {
+    dev->regs->IFCR = (1U << (4 * (tube - 1)));
+}
+
+/**
+ * @brief Deprecated
+ * STM32F1 mode flags for dma_setup_xfer(). Use dma_tube_cfg() instead.
+ * @see dma_tube_cfg()
+ */
+typedef enum dma_mode_flags {
+    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
+    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
+    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
+    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
+    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
+    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
+    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
+    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+} dma_mode_flags;
+
+/* Keep this around for backwards compatibility, but it's deprecated.
+ * New code should use dma_tube_cfg() instead.
+ *
+ * (It's not possible to fully configure a DMA stream on F2 with just
+ * this information, so this interface is too tied to the F1.) */
+__deprecated
+void dma_setup_transfer(dma_dev       *dev,
+                        dma_channel    channel,
+                        __io void     *peripheral_address,
+                        dma_xfer_size  peripheral_size,
+                        __io void     *memory_address,
+                        dma_xfer_size  memory_size,
+                        uint32         mode);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif

libmaple/stm32f1/include/series/exti.h

@@ -0,0 +1,46 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/exti.h
+ * @brief STM32F1 external interrupts
+ */
+
+#ifndef _LIBMAPLE_STM32F1_EXTI_H_
+#define _LIBMAPLE_STM32F1_EXTI_H_
+
+#ifdef __cpluspus
+extern "C" {
+#endif
+
+struct exti_reg_map;
+#define EXTI_BASE ((struct exti_reg_map*)0x40010400)
+
+#ifdef __cpluspus
+}
+#endif
+
+#endif

libmaple/flash.h → libmaple/stm32f1/include/series/flash.h

@@ -25,21 +25,28 @@
  *****************************************************************************/
 
 /**
- * @file flash.h
- * @brief STM32 Medium and high density Flash register map and setup
- * routines
+ * @file libmaple/stm32f1/include/series/flash.h
+ * @brief STM32F1 Flash header.
+ *
+ * Provides register map, base pointer, and register bit definitions
+ * for the Flash controller on the STM32F1 line, along with
+ * series-specific configuration values.
  */
 
-#include "libmaple_types.h"
-
-#ifndef _FLASH_H_
-#define _FLASH_H_
+#ifndef _LIBMAPLE_STM32F1_FLASH_H_
+#define _LIBMAPLE_STM32F1_FLASH_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
-/** Flash register map type */
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Register map
+ */
+
+/** @brief STM32F1 Flash register map type */
 typedef struct flash_reg_map {
     __io uint32 ACR;            /**< Access control register */
     __io uint32 KEYR;           /**< Key register */
@@ -51,7 +58,6 @@ typedef struct flash_reg_map {
     __io uint32 WRPR;           /**< Write protection register */
 } flash_reg_map;
 
-/** Flash register map base pointer */
 #define FLASH_BASE                      ((struct flash_reg_map*)0x40022000)
 
 /*
@@ -64,9 +70,9 @@ typedef struct flash_reg_map {
 #define FLASH_ACR_PRFTBE_BIT            4
 #define FLASH_ACR_HLFCYA_BIT            3
 
-#define FLASH_ACR_PRFTBS                BIT(FLASH_ACR_PRFTBS_BIT)
-#define FLASH_ACR_PRFTBE                BIT(FLASH_ACR_PRFTBE_BIT)
-#define FLASH_ACR_HLFCYA                BIT(FLASH_ACR_HLFCYA_BIT)
+#define FLASH_ACR_PRFTBS                (1U << FLASH_ACR_PRFTBS_BIT)
+#define FLASH_ACR_PRFTBE                (1U << FLASH_ACR_PRFTBE_BIT)
+#define FLASH_ACR_HLFCYA                (1U << FLASH_ACR_HLFCYA_BIT)
 #define FLASH_ACR_LATENCY               0x7
 
 /* Status register */
@@ -76,10 +82,10 @@ typedef struct flash_reg_map {
 #define FLASH_SR_PGERR_BIT              2
 #define FLASH_SR_BSY_BIT                0
 
-#define FLASH_SR_EOP                    BIT(FLASH_SR_EOP_BIT)
-#define FLASH_SR_WRPRTERR               BIT(FLASH_SR_WRPRTERR_BIT)
-#define FLASH_SR_PGERR                  BIT(FLASH_SR_PGERR_BIT)
-#define FLASH_SR_BSY                    BIT(FLASH_SR_BSY_BIT)
+#define FLASH_SR_EOP                    (1U << FLASH_SR_EOP_BIT)
+#define FLASH_SR_WRPRTERR               (1U << FLASH_SR_WRPRTERR_BIT)
+#define FLASH_SR_PGERR                  (1U << FLASH_SR_PGERR_BIT)
+#define FLASH_SR_BSY                    (1U << FLASH_SR_BSY_BIT)
 
 /* Control register */
 
@@ -94,16 +100,16 @@ typedef struct flash_reg_map {
 #define FLASH_CR_PER_BIT                1
 #define FLASH_CR_PG_BIT                 0
 
-#define FLASH_CR_EOPIE                  BIT(FLASH_CR_EOPIE_BIT)
-#define FLASH_CR_ERRIE                  BIT(FLASH_CR_ERRIE_BIT)
-#define FLASH_CR_OPTWRE                 BIT(FLASH_CR_OPTWRE_BIT)
-#define FLASH_CR_LOCK                   BIT(FLASH_CR_LOCK_BIT)
-#define FLASH_CR_STRT                   BIT(FLASH_CR_STRT_BIT)
-#define FLASH_CR_OPTER                  BIT(FLASH_CR_OPTER_BIT)
-#define FLASH_CR_OPTPG                  BIT(FLASH_CR_OPTPG_BIT)
-#define FLASH_CR_MER                    BIT(FLASH_CR_MER_BIT)
-#define FLASH_CR_PER                    BIT(FLASH_CR_PER_BIT)
-#define FLASH_CR_PG                     BIT(FLASH_CR_PG_BIT)
+#define FLASH_CR_EOPIE                  (1U << FLASH_CR_EOPIE_BIT)
+#define FLASH_CR_ERRIE                  (1U << FLASH_CR_ERRIE_BIT)
+#define FLASH_CR_OPTWRE                 (1U << FLASH_CR_OPTWRE_BIT)
+#define FLASH_CR_LOCK                   (1U << FLASH_CR_LOCK_BIT)
+#define FLASH_CR_STRT                   (1U << FLASH_CR_STRT_BIT)
+#define FLASH_CR_OPTER                  (1U << FLASH_CR_OPTER_BIT)
+#define FLASH_CR_OPTPG                  (1U << FLASH_CR_OPTPG_BIT)
+#define FLASH_CR_MER                    (1U << FLASH_CR_MER_BIT)
+#define FLASH_CR_PER                    (1U << FLASH_CR_PER_BIT)
+#define FLASH_CR_PG                     (1U << FLASH_CR_PG_BIT)
 
 /* Option byte register */
 
@@ -116,27 +122,28 @@ typedef struct flash_reg_map {
 #define FLASH_OBR_DATA1                 (0xFF << 18)
 #define FLASH_OBR_DATA0                 (0xFF << 10)
 #define FLASH_OBR_USER                  0x3FF
-#define FLASH_OBR_nRST_STDBY            BIT(FLASH_OBR_nRST_STDBY_BIT)
-#define FLASH_OBR_nRST_STOP             BIT(FLASH_OBR_nRST_STOP_BIT)
-#define FLASH_OBR_WDG_SW                BIT(FLASH_OBR_WDG_SW_BIT)
-#define FLASH_OBR_RDPRT                 BIT(FLASH_OBR_RDPRT_BIT)
-#define FLASH_OBR_OPTERR                BIT(FLASH_OBR_OPTERR_BIT)
+#define FLASH_OBR_nRST_STDBY            (1U << FLASH_OBR_nRST_STDBY_BIT)
+#define FLASH_OBR_nRST_STOP             (1U << FLASH_OBR_nRST_STOP_BIT)
+#define FLASH_OBR_WDG_SW                (1U << FLASH_OBR_WDG_SW_BIT)
+#define FLASH_OBR_RDPRT                 (1U << FLASH_OBR_RDPRT_BIT)
+#define FLASH_OBR_OPTERR                (1U << FLASH_OBR_OPTERR_BIT)
 
 /*
- * Setup routines
+ * Series-specific configuration values.
  */
 
-#define FLASH_WAIT_STATE_0              0x0
-#define FLASH_WAIT_STATE_1              0x1
-#define FLASH_WAIT_STATE_2              0x2
+#define FLASH_SAFE_WAIT_STATES          FLASH_WAIT_STATE_2
 
-void flash_enable_prefetch(void);
-void flash_set_latency(uint32 wait_states);
+/* Flash memory features available via ACR */
+enum {
+    FLASH_PREFETCH   = 0x10,
+    FLASH_HALF_CYCLE = 0x8,
+    FLASH_ICACHE     = 0x0,     /* Not available on STM32F1 */
+    FLASH_DCACHE     = 0x0,     /* Not available on STM32F1 */
+};
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif
-
-

libmaple/gpio.h → libmaple/stm32f1/include/series/gpio.h

@@ -2,6 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -25,22 +26,22 @@
 *****************************************************************************/
 
 /**
- *  @file gpio.h
- *
- *  @brief General purpose I/O (GPIO) and Alternate Function I/O
- *         (AFIO) prototypes, defines, and inlined access functions.
+ * @file libmaple/stm32f1/include/series/gpio.h
+ * @brief STM32F1 GPIO and AFIO support.
+ * General purpose I/O (GPIO) and Alternate Function I/O (AFIO).
  */
 
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include "libmaple.h"
-#include "rcc.h"
+#ifndef _LIBMAPLE_STM32F1_GPIO_H_
+#define _LIBMAPLE_STM32F1_GPIO_H_
 
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+#include <libmaple/stm32.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/exti.h>
+
 /*
  * GPIO register maps and devices
  */
@@ -56,46 +57,22 @@ typedef struct gpio_reg_map {
     __io uint32 LCKR;     /**< Port configuration lock register */
 } gpio_reg_map;
 
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
-    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
-    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
-    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
-    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
-#ifdef STM32_HIGH_DENSITY
-    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
-    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
-    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
-#endif
-} afio_exti_port;
-
-/** GPIO device type */
-typedef struct gpio_dev {
-    gpio_reg_map *regs;       /**< Register map */
-    rcc_clk_id clk_id;        /**< RCC clock information */
-    afio_exti_port exti_port; /**< AFIO external interrupt port value */
-} gpio_dev;
-
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
+struct gpio_dev;
+extern struct gpio_dev gpioa;
+extern struct gpio_dev* const GPIOA;
+extern struct gpio_dev gpiob;
+extern struct gpio_dev* const GPIOB;
+extern struct gpio_dev gpioc;
+extern struct gpio_dev* const GPIOC;
+extern struct gpio_dev gpiod;
+extern struct gpio_dev* const GPIOD;
 #ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
-extern gpio_dev* const GPIOF;
-extern gpio_dev gpiog;
-extern gpio_dev* const GPIOG;
+extern struct gpio_dev gpioe;
+extern struct gpio_dev* const GPIOE;
+extern struct gpio_dev gpiof;
+extern struct gpio_dev* const GPIOF;
+extern struct gpio_dev gpiog;
+extern struct gpio_dev* const GPIOG;
 #endif
 
 /** GPIO port A register map base pointer */
@@ -106,14 +83,12 @@ extern gpio_dev* const GPIOG;
 #define GPIOC_BASE                      ((struct gpio_reg_map*)0x40011000)
 /** GPIO port D register map base pointer */
 #define GPIOD_BASE                      ((struct gpio_reg_map*)0x40011400)
-#ifdef STM32_HIGH_DENSITY
 /** GPIO port E register map base pointer */
 #define GPIOE_BASE                      ((struct gpio_reg_map*)0x40011800)
 /** GPIO port F register map base pointer */
 #define GPIOF_BASE                      ((struct gpio_reg_map*)0x40011C00)
 /** GPIO port G register map base pointer */
 #define GPIOG_BASE                      ((struct gpio_reg_map*)0x40012000)
-#endif
 
 /*
  * GPIO register bit definitions
@@ -136,86 +111,33 @@ extern gpio_dev* const GPIOG;
 #define GPIO_CR_MODE_OUTPUT_50MHZ       0x3
 
 /**
- * @brief GPIO Pin modes.
+ * @brief GPIO pin modes.
  *
  * These only allow for 50MHZ max output speeds; if you want slower,
  * use direct register access.
  */
 typedef enum gpio_pin_mode {
-    GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */
-    GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */
-    GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output push-pull. */
-    GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output open drain. */
-    GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG |
-                         GPIO_CR_MODE_INPUT), /**< Analog input. */
-    GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING |
-                           GPIO_CR_MODE_INPUT), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD |
-                     GPIO_CR_MODE_INPUT), /**< Input pull-down. */
-    GPIO_INPUT_PU /**< Input pull-up. */
-    /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */
+    /** Output push-pull. */
+    GPIO_OUTPUT_PP      = GPIO_CR_CNF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ,
+    /** Output open-drain. */
+    GPIO_OUTPUT_OD      = GPIO_CR_CNF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ,
+    /** Alternate function output push-pull. */
+    GPIO_AF_OUTPUT_PP   = GPIO_CR_CNF_AF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ,
+    /** Alternate function output open drain. */
+    GPIO_AF_OUTPUT_OD   = GPIO_CR_CNF_AF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ,
+    /** Analog input. */
+    GPIO_INPUT_ANALOG   = GPIO_CR_CNF_INPUT_ANALOG | GPIO_CR_MODE_INPUT,
+    /** Input floating. */
+    GPIO_INPUT_FLOATING = GPIO_CR_CNF_INPUT_FLOATING | GPIO_CR_MODE_INPUT,
+    /** Input pull-down. */
+    GPIO_INPUT_PD       = GPIO_CR_CNF_INPUT_PU_PD | GPIO_CR_MODE_INPUT,
+    /** Input pull-up. */
+    GPIO_INPUT_PU, /* (treated a special case, for ODR twiddling) */
 } gpio_pin_mode;
 
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRR = BIT(pin);
-    } else {
-        dev->regs->BRR = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
+/* Hacks for F2: */
+#define GPIO_MODE_ANALOG GPIO_INPUT_ANALOG
+#define GPIO_MODE_OUTPUT GPIO_OUTPUT_PP
 
 /*
  * AFIO register map
@@ -223,19 +145,14 @@ static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
 
 /** AFIO register map */
 typedef struct afio_reg_map {
-    __io uint32 EVCR;        /**< Event control register.  */
-    __io uint32 MAPR;        /**< AF remap and debug I/O configuration
-                                register. */
-    __io uint32 EXTICR1;     /**< External interrupt configuration
-                                register 1. */
-    __io uint32 EXTICR2;     /**< External interrupt configuration
-                                register 2. */
-    __io uint32 EXTICR3;     /**< External interrupt configuration
-                                register 3. */
-    __io uint32 EXTICR4;     /**< External interrupt configuration
-                                register 4. */
-    __io uint32 MAPR2;       /**< AF remap and debug I/O configuration
-                                register 2. */
+    __io uint32 EVCR;    /**< Event control register.  */
+    __io uint32 MAPR;    /**< AF remap and debug I/O configuration register. */
+    __io uint32 EXTICR1; /**< External interrupt configuration register 1. */
+    __io uint32 EXTICR2; /**< External interrupt configuration register 2. */
+    __io uint32 EXTICR3; /**< External interrupt configuration register 3. */
+    __io uint32 EXTICR4; /**< External interrupt configuration register 4. */
+    __io uint32 MAPR2;   /**<
+                          * AF remap and debug I/O configuration register 2. */
 } afio_reg_map;
 
 /** AFIO register map base pointer. */
@@ -277,17 +194,17 @@ typedef struct afio_reg_map {
 #define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
 #define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
 #define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
-#define AFIO_MAPR_PD01_REMAP                   BIT(15)
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP           (1U << 20)
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           (1U << 19)
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP           (1U << 18)
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           (1U << 17)
+#define AFIO_MAPR_TIM5CH4_IREMAP               (1U << 16)
+#define AFIO_MAPR_PD01_REMAP                   (1U << 15)
 #define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
 #define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
 #define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
 #define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
+#define AFIO_MAPR_TIM4_REMAP                   (1U << 12)
 #define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
 #define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
 #define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
@@ -305,10 +222,10 @@ typedef struct afio_reg_map {
 #define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
 #define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
 #define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP                 BIT(3)
-#define AFIO_MAPR_USART1_REMAP                 BIT(2)
-#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
-#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
+#define AFIO_MAPR_USART2_REMAP                 (1U << 3)
+#define AFIO_MAPR_USART1_REMAP                 (1U << 2)
+#define AFIO_MAPR_I2C1_REMAP                   (1U << 1)
+#define AFIO_MAPR_SPI1_REMAP                   (1U << 0)
 
 /* External interrupt configuration register 1 */
 
@@ -382,12 +299,12 @@ typedef struct afio_reg_map {
 
 /* AF remap and debug I/O configuration register 2 */
 
-#define AFIO_MAPR2_FSMC_NADV            BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
+#define AFIO_MAPR2_FSMC_NADV            (1U << 10)
+#define AFIO_MAPR2_TIM14_REMAP          (1U << 9)
+#define AFIO_MAPR2_TIM13_REMAP          (1U << 8)
+#define AFIO_MAPR2_TIM11_REMAP          (1U << 7)
+#define AFIO_MAPR2_TIM10_REMAP          (1U << 6)
+#define AFIO_MAPR2_TIM9_REMAP           (1U << 5)
 
 /*
  * AFIO convenience routines
@@ -395,95 +312,67 @@ typedef struct afio_reg_map {
 
 void afio_init(void);
 
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
-    AFIO_EXTI_0,                /**< External interrupt line 0. */
-    AFIO_EXTI_1,                /**< External interrupt line 1. */
-    AFIO_EXTI_2,                /**< External interrupt line 2. */
-    AFIO_EXTI_3,                /**< External interrupt line 3. */
-    AFIO_EXTI_4,                /**< External interrupt line 4. */
-    AFIO_EXTI_5,                /**< External interrupt line 5. */
-    AFIO_EXTI_6,                /**< External interrupt line 6. */
-    AFIO_EXTI_7,                /**< External interrupt line 7. */
-    AFIO_EXTI_8,                /**< External interrupt line 8. */
-    AFIO_EXTI_9,                /**< External interrupt line 9. */
-    AFIO_EXTI_10,               /**< External interrupt line 10. */
-    AFIO_EXTI_11,               /**< External interrupt line 11. */
-    AFIO_EXTI_12,               /**< External interrupt line 12. */
-    AFIO_EXTI_13,               /**< External interrupt line 13. */
-    AFIO_EXTI_14,               /**< External interrupt line 14. */
-    AFIO_EXTI_15,               /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
 /* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
  * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2            (1 << 31)
+#define AFIO_REMAP_USE_MAPR2            (1U << 31)
 
 /**
  * @brief Available peripheral remaps.
  * @see afio_remap()
  */
 typedef enum afio_remap_peripheral {
-    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
-        ADC 2 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
-        ADC 2 external trigger injected conversion remapping */
-    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
-        ADC 1 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
-        ADC 1 external trigger injected conversion remapping */
-    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
-        Timer 5 channel 4 internal remapping */
-    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
-        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
-        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
-    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
-        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
-    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
-        Timer 4 remapping */
-    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
-        Timer 3 partial remapping */
-    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
-        Timer 3 full remapping */
-    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
-        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
-        on PA2, CH4 on PA3) */
-    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
-        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
-        on PB10, CH4 on PB11) */
-    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
-        Timer 2 full remapping */
-    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
-        USART 2 remapping */
-    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
-        USART 1 remapping */
-    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
-        I2C 1 remapping */
-    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
-        SPI 1 remapping */
-    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        NADV signal not connected */
-    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 14 remapping */
-    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 13 remapping */
-    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 11 remapping */
-    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 10 remapping */
-    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
-                                AFIO_REMAP_USE_MAPR2) /**<
-        Timer 9 */
+     /** ADC 2 external trigger regular conversion remapping */
+    AFIO_REMAP_ADC2_ETRGREG   = AFIO_MAPR_ADC2_ETRGREG_REMAP,
+     /** ADC 2 external trigger injected conversion remapping */
+    AFIO_REMAP_ADC2_ETRGINJ   = AFIO_MAPR_ADC2_ETRGINJ_REMAP,
+    /** ADC 1 external trigger regular conversion remapping */
+    AFIO_REMAP_ADC1_ETRGREG   = AFIO_MAPR_ADC1_ETRGREG_REMAP,
+    /** ADC 1 external trigger injected conversion remapping */
+    AFIO_REMAP_ADC1_ETRGINJ   = AFIO_MAPR_ADC1_ETRGINJ_REMAP,
+    /** Timer 5 channel 4 internal remapping */
+    AFIO_REMAP_TIM5CH4_I      = AFIO_MAPR_TIM5CH4_IREMAP,
+    /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+    AFIO_REMAP_PD01           = AFIO_MAPR_PD01_REMAP,
+    /** CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
+    AFIO_REMAP_CAN_1          = AFIO_MAPR_CAN_REMAP_PB8_PB9,
+    /** CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
+    AFIO_REMAP_CAN_2          = AFIO_MAPR_CAN_REMAP_PD0_PD1,
+    /** Timer 4 remapping */
+    AFIO_REMAP_TIM4           = AFIO_MAPR_TIM4_REMAP,
+    /** Timer 3 partial remapping */
+    AFIO_REMAP_TIM3_PARTIAL   = AFIO_MAPR_TIM3_REMAP_PARTIAL,
+    /** Timer 3 full remapping */
+    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL,
+    /**
+     * Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3,
+     * CH3 on                                      PA2, CH4 on PA3) */
+    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3,
+    /**
+     * Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1,
+     * CH3 on                                      PB10, CH4 on PB11) */
+    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11,
+    /** Timer 2 full remapping */
+    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL,
+    /** USART 2 remapping */
+    AFIO_REMAP_USART2         = AFIO_MAPR_USART2_REMAP,
+    /** USART 1 remapping */
+    AFIO_REMAP_USART1         = AFIO_MAPR_USART1_REMAP,
+    /** I2C 1 remapping */
+    AFIO_REMAP_I2C1           = AFIO_MAPR_I2C1_REMAP,
+    /** SPI 1 remapping */
+    AFIO_REMAP_SPI1           = AFIO_MAPR_SPI1_REMAP,
+    /** NADV signal not connected */
+    AFIO_REMAP_FSMC_NADV      = AFIO_MAPR2_FSMC_NADV | AFIO_REMAP_USE_MAPR2,
+    /** Timer 14 remapping */
+    AFIO_REMAP_TIM14          = AFIO_MAPR2_TIM14_REMAP | AFIO_REMAP_USE_MAPR2,
+    /** Timer 13 remapping */
+    AFIO_REMAP_TIM13          = AFIO_MAPR2_TIM13_REMAP | AFIO_REMAP_USE_MAPR2,
+    /** Timer 11 remapping */
+    AFIO_REMAP_TIM11          = AFIO_MAPR2_TIM11_REMAP | AFIO_REMAP_USE_MAPR2,
+    /** Timer 10 remapping */
+    AFIO_REMAP_TIM10          = AFIO_MAPR2_TIM10_REMAP | AFIO_REMAP_USE_MAPR2,
+    /** Timer 9 remapping */
+    AFIO_REMAP_TIM9           = AFIO_MAPR2_TIM9_REMAP | AFIO_REMAP_USE_MAPR2,
 } afio_remap_peripheral;
 
 void afio_remap(afio_remap_peripheral p);
@@ -497,16 +386,14 @@ void afio_remap(afio_remap_peripheral p);
  * @see afio_cfg_debug_ports()
  */
 typedef enum afio_debug_cfg {
-    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
-                                   Full Serial Wire and JTAG debug */
-    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
-                                   Full Serial Wire and JTAG, but no NJTRST. */
-    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
-                                   Serial Wire debug only (JTAG-DP disabled,
-                                   SW-DP enabled) */
-    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
-                                   No debug; all JTAG and SW pins are free
-                                   for use as GPIOs. */
+    /** Full Serial Wire and JTAG debug */
+    AFIO_DEBUG_FULL_SWJ          = AFIO_MAPR_SWJ_CFG_FULL_SWJ,
+    /** Full Serial Wire and JTAG, but no NJTRST. */
+    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST,
+    /** Serial Wire debug only (JTAG-DP disabled, SW-DP enabled) */
+    AFIO_DEBUG_SW_ONLY           = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW,
+    /** No debug; all JTAG and SW pins are free for use as GPIOs. */
+    AFIO_DEBUG_NONE              = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW,
 } afio_debug_cfg;
 
 /**
@@ -519,9 +406,88 @@ static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
     *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
 }
 
+/*
+ * Deprecated bits
+ */
+
+/**
+ * @brief Deprecated. Use exti_cfg instead.
+ *
+ * In previous versions of libmaple, exti_attach_interrupt() took an
+ * afio_exti_port argument; afio_exti_port was also a member of struct
+ * gpio_dev. This isn't portable, so we now use exti_cfg
+ * instead. This typedef (and the macros AFIO_EXTI_PA, ...,
+ * AFIO_EXTI_PG) exist to preserve backwards compatibility.
+ */
+typedef exti_cfg afio_exti_port;
+
+/** Deprecated. Use EXTI_PA instead. */
+#define AFIO_EXTI_PA EXTI_PA
+/** Deprecated. Use EXTI_PB instead. */
+#define AFIO_EXTI_PB EXTI_PB
+/** Deprecated. Use EXTI_PC instead. */
+#define AFIO_EXTI_PC EXTI_PC
+/** Deprecated. Use EXTI_PD instead. */
+#define AFIO_EXTI_PD EXTI_PD
+/** Deprecated. Use EXTI_PE instead. */
+#define AFIO_EXTI_PE EXTI_PE
+/** Deprecated. Use EXTI_PF instead. */
+#define AFIO_EXTI_PF EXTI_PF
+/** Deprecated. Use EXTI_PG instead. */
+#define AFIO_EXTI_PG EXTI_PG
+
+/**
+ * @brief Deprecated. Use exti_num instead.
+ *
+ * In previous versions of libmaple, exti_attach_interrupt() took an
+ * afio_exti_num argument. This isn't portable, so we use exti_num
+ * instead. This typedef (and the macros AFIO_EXTI_0, ...,
+ * AFIO_EXTI_15) exist to preserve backwards compatibility.
+ */
+typedef exti_num afio_exti_num;
+
+/** Deprecated. Use EXTI0 instead. */
+#define AFIO_EXTI_0 EXTI0
+/** Deprecated. Use EXTI1 instead. */
+#define AFIO_EXTI_1 EXTI1
+/** Deprecated. Use EXTI2 instead. */
+#define AFIO_EXTI_2 EXTI2
+/** Deprecated. Use EXTI3 instead. */
+#define AFIO_EXTI_3 EXTI3
+/** Deprecated. Use EXTI4 instead. */
+#define AFIO_EXTI_4 EXTI4
+/** Deprecated. Use EXTI5 instead. */
+#define AFIO_EXTI_5 EXTI5
+/** Deprecated. Use EXTI6 instead. */
+#define AFIO_EXTI_6 EXTI6
+/** Deprecated. Use EXTI7 instead. */
+#define AFIO_EXTI_7 EXTI7
+/** Deprecated. Use EXTI8 instead. */
+#define AFIO_EXTI_8 EXTI8
+/** Deprecated. Use EXTI9 instead. */
+#define AFIO_EXTI_9 EXTI9
+/** Deprecated. Use EXTI10 instead. */
+#define AFIO_EXTI_10 EXTI10
+/** Deprecated. Use EXTI11 instead. */
+#define AFIO_EXTI_11 EXTI11
+/** Deprecated. Use EXTI12 instead. */
+#define AFIO_EXTI_12 EXTI12
+/** Deprecated. Use EXTI13 instead. */
+#define AFIO_EXTI_13 EXTI13
+/** Deprecated. Use EXTI14 instead. */
+#define AFIO_EXTI_14 EXTI14
+/** Deprecated. Use EXTI15 instead. */
+#define AFIO_EXTI_15 EXTI15
+
+/**
+ * @brief Deprecated. Use exti_select(exti, port) instead.
+ */
+static __always_inline void afio_exti_select(exti_num exti, exti_cfg port) {
+    exti_select(exti, port);
+}
+
 #ifdef __cplusplus
 }
 #endif
 
 #endif
-

libmaple/stm32f1/include/series/i2c.h

@@ -0,0 +1,85 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung (from <libmaple/i2c.h>).
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/stm32f1/include/series/i2c.h
+ * @brief STM32F1 I2C
+ */
+
+#ifndef _LIBMAPLE_STM32F1_I2C_H_
+#define _LIBMAPLE_STM32F1_I2C_H_
+
+#include <libmaple/i2c_common.h>
+#include <libmaple/gpio.h>
+#include <libmaple/stm32.h>
+
+/*
+ * Register maps
+ */
+
+struct i2c_reg_map;
+
+/** STM32F1 I2C1 register map base pointer */
+#define I2C1_BASE               ((struct i2c_reg_map*)0x40005400)
+/** STM32F1 I2C2 register map base pointer */
+#define I2C2_BASE               ((struct i2c_reg_map*)0x40005800)
+
+/*
+ * Devices
+ */
+
+extern i2c_dev* const I2C1;
+extern i2c_dev* const I2C2;
+
+/*
+ * For internal use
+ */
+
+static inline uint32 _i2c_bus_clk(i2c_dev *dev) {
+    /* Both I2C peripherals are on APB1 */
+    return STM32_PCLK1 / (1000 * 1000);
+}
+
+#define _I2C_HAVE_IRQ_FIXUP 1
+void _i2c_irq_priority_fixup(i2c_dev *dev);
+
+/*
+ * Deprecated functionality
+ */
+
+/* Flag to use alternate pin mapping in i2c_master_enable(). */
+#define _I2C_HAVE_DEPRECATED_I2C_REMAP 1
+#define I2C_REMAP 0x4
+static inline void _i2c_handle_remap(i2c_dev *dev, uint32 flags) {
+    if ((dev == I2C1) && (flags & I2C_REMAP)) {
+        afio_remap(AFIO_REMAP_I2C1);
+        I2C1->sda_pin = 9;
+        I2C1->scl_pin = 8;
+    }
+}
+
+#endif  /* _LIBMAPLE_STM32F1_I2C_H_ */