302 lines
8.9 KiB
C
Executable file
302 lines
8.9 KiB
C
Executable file
/*-------------------------------------------------------------------------
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Register Declarations for 87C764
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Written By - Robert Lacoste, robert_lacoste@yahoo.fr
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based upon reg51.h written by Sandeep Dutta
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Registers are taken from the Phillips Semiconductor
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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In other words, you are welcome to use, share and improve this program.
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You are forbidden to forbid anyone else to use, share and improve
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what you give them. Help stamp out software-hoarding!
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-------------------------------------------------------------------------*/
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#ifndef REGC764_H
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#define REGC764_H
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/* Special Function Registers */
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sfr at 0x80 P0 ; // Port 0
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sfr at 0x81 SP ; // Stack Pointer
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sfr at 0x82 DPL ; // Data Pointer Low
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sfr at 0x83 DPH ; // Data Pointer High
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sfr at 0x84 P0M1 ; // Port 0 output mode 1
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sfr at 0x85 P0M2 ; // Port 0 output mode 2
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sfr at 0x86 KBI ; // Keyboard interrupt
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sfr at 0x87 PCON ; // Power Control
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sfr at 0x88 TCON ; // Timer Control
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sfr at 0x89 TMOD ; // Timer Mode
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sfr at 0x8A TL0 ; // Timer Low 0
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sfr at 0x8B TL1 ; // Timer Low 1
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sfr at 0x8C TH0 ; // Timer High 0
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sfr at 0x8D TH1 ; // Timer High 1
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sfr at 0x90 P1 ; // Port 1
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sfr at 0x91 P1M1 ; // Port 1 output mode 1
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sfr at 0x92 P1M2 ; // Port 1 output mode 2
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sfr at 0x95 DIVM ; // CPU clock divide by N control
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sfr at 0x98 SCON ; // Serial Control
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sfr at 0x99 SBUF ; // Serial Data Buffer
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sfr at 0xA0 P2 ; // Port 2
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sfr at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx)
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sfr at 0xA4 P2M1 ; // Port 2 output mode 1
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sfr at 0xA5 P2M2 ; // Port 2 output mode 2
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sfr at 0xA6 WDRST ; // Watchdog reset register
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sfr at 0xA7 WDCON ; // Watchdog control register
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sfr at 0xA8 IEN0 ; // Interrupt Enable 0
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sfr at 0xA9 SADDR ; // Serial slave Address
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sfr at 0xAC CMP1 ; // Comparator 1 control register
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sfr at 0xAD CMP2 ; // Comparator 2 control register
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sfr at 0xB7 IP0H ; // Interrupt Priority 0 High
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sfr at 0xB8 IP0 ; // Interrupt Priority 0
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sfr at 0xB9 SADEN ; // Serial slave Address Mask
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sfr at 0xC8 I2CFG ; // I2C configuration register
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sfr at 0xD0 PSW ; // Program Status Word
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sfr at 0xD8 I2CON ; // I2C control register
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sfr at 0xD9 I2DAT ; // I2C data register
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sfr at 0xE0 ACC ; // Accumulator
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sfr at 0xE8 IEN1 ; // Interrupt enable 1
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sfr at 0xF0 B ; // B Register
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sfr at 0xF6 PT0AD ; // Port 0 digital input disable
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sfr at 0xF7 IP1H ; // Interrupt Priority 1 High
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sfr at 0xF8 IP1 ; // Interrupt Priority 1
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/* Bit Addressable Registers */
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/* P0 */
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sbit at 0x80 P0_0 ; // Also CMP2
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sbit at 0x81 P0_1 ; // Also CIN2B
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sbit at 0x82 P0_2 ; // Also CIN2A
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sbit at 0x83 P0_3 ; // Also CIN1B
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sbit at 0x84 P0_4 ; // Also CIN1A
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sbit at 0x85 P0_5 ; // Also CMPREF
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sbit at 0x86 P0_6 ; // Also CMP1
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sbit at 0x87 P0_7 ; // Also T1
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/* TCON */
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sbit at 0x88 IT0 ; // External Interrupt 0 Type
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sbit at 0x89 IE0 ; // External Interrupt 0 Edge Flag
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sbit at 0x8A IT1 ; // External Interrupt 1 Type
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sbit at 0x8B IE1 ; // External Interrupt 1 Edge Flag
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sbit at 0x8C TR0 ; // Timer 0 Run Control
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sbit at 0x8D TF0 ; // Timer 0 Overflow Flag
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sbit at 0x8E TR1 ; // Timer 1 Run Control
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sbit at 0x8F TF1 ; // Timer 1 Overflow Flag
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/* P1 */
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sbit at 0x90 P1_0 ; // Also TxD
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sbit at 0x91 P1_1 ; // Also RxD
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sbit at 0x92 P1_2 ; // Also T0
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sbit at 0x93 P1_3 ; // Also INT0
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sbit at 0x94 P1_4 ; // Also INT1
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sbit at 0x95 P1_5 ; // Also RST
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sbit at 0x96 P1_6 ;
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sbit at 0x97 P1_7 ;
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/* SCON */
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sbit at 0x98 RI ; // Receive Interrupt Flag
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sbit at 0x99 TI ; // Transmit Interrupt Flag
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sbit at 0x9A RB8 ; // Receive Bit 8
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sbit at 0x9B TB8 ; // Transmit Bit 8
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sbit at 0x9C REN ; // Receiver Enable
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sbit at 0x9D SM2 ; // Serial Mode Control Bit 2
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sbit at 0x9E SM1 ; // Serial Mode Control Bit 1
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sbit at 0x9F SM0 ; // Serial Mode Control Bit 0
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/* P2 */
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sbit at 0xA0 P2_0 ; // Also X2
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sbit at 0xA1 P2_1 ; // Also X1
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/* IEN0 */
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sbit at 0xA8 EX0 ; // External Interrupt 0 Enable
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sbit at 0xA9 ET0 ; // Timer 0 Interrupt Enable
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sbit at 0xAA EX1 ; // External Interrupt 1 Enable
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sbit at 0xAB ET1 ; // Timer 1 Interrupt Enable
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sbit at 0xAC ES ; // Serial Port Interrupt Enable
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sbit at 0xAD EBO ; // Brownout Interrupt Enable
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sbit at 0xAE EWD ; // Watchdog Interrupt Enable
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sbit at 0xAF EA ; // Global Interrupt Enable
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/* IP0 */
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sbit at 0xB8 PX0 ; // External Interrupt 0 Priority
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sbit at 0xB9 PT0 ; // Timer 0 Interrupt Priority
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sbit at 0xBA PX1 ; // External Interrupt 1 Priority
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sbit at 0xBB PT1 ; // Timer 1 Interrupt Priority
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sbit at 0xBC PS ; // Serial Port Interrupt Priority
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sbit at 0xBD PB0 ; // Brownout Interrupt Priority
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sbit at 0xBE PWD ; // Watchdog Interrupt Priority
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/* I2CFG */
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sbit at 0xC8 CT0 ; // Clock Time Select 0
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sbit at 0xC9 CT1 ; // Clock Time Select 1
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sbit at 0xCC TIRUN ; // Timer I Run Enable
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sbit at 0xCD CLRTI ; // Clear Timer I
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sbit at 0xCE MASTRQ; // Master Request
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sbit at 0xCF SLAVEN; // Slave Enable
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/* PSW */
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sbit at 0xD0 P ; // Accumulator Parity Flag
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sbit at 0xD1 F1 ; // Flag 1
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sbit at 0xD2 OV ; // Overflow Flag
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sbit at 0xD3 RS0 ; // Register Bank Select 0
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sbit at 0xD4 RS1 ; // Register Bank Select 1
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sbit at 0xD5 F0 ; // Flag 0
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sbit at 0xD6 AC ; // Auxiliary Carry Flag
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sbit at 0xD7 CY ; // Carry Flag
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/* I2CON */
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sbit at 0xD8 XSTP ;
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sbit at 0xD9 MASTER;// Master Status
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sbit at 0xDA STP ; // Stop Detect Flag
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sbit at 0xDB STR ; // Start Detect Flag
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sbit at 0xDC ARL ; // Arbitration Loss Flag
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sbit at 0xDD DRDY ; // Data Ready Flag
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sbit at 0xDE ATN ; // Attention: I2C Interrupt Flag
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sbit at 0xDF RDAT ; // I2C Read Data
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/* ACC */
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sbit at 0xE0 ACC_0;
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sbit at 0xE1 ACC_1;
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sbit at 0xE2 ACC_2;
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sbit at 0xE3 ACC_3;
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sbit at 0xE4 ACC_4;
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sbit at 0xE5 ACC_5;
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sbit at 0xE6 ACC_6;
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sbit at 0xE7 ACC_7;
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/* IEN1 */
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sbit at 0xE8 EI2 ; // I2C Interrupt Enable
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sbit at 0xE9 EKB ; // Keyboard Interrupt Enable
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sbit at 0xEA EC2 ; // Comparator 2 Interrupt Enable
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sbit at 0xED EC1 ; // Comparator 1 Interrupt Enable
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sbit at 0xEF ETI ; // Timer I Interrupt Enable
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/* B */
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sbit at 0xF0 B_0;
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sbit at 0xF1 B_1;
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sbit at 0xF2 B_2;
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sbit at 0xF3 B_3;
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sbit at 0xF4 B_4;
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sbit at 0xF5 B_5;
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sbit at 0xF6 B_6;
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sbit at 0xF7 B_7;
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/* IP1 */
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sbit at 0xF8 PI2; // I2C Interrupt Priority
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sbit at 0xF9 PKB; // Keyboard Interrupt Priority
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sbit at 0xFA PC2; // Comparator 2 Interrupt Priority
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sbit at 0xFD PC1; // Comparator 1 Interrupt Priority
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sbit at 0xFF PTI; // Timer I Interrupt Priority
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/* Bitmasks for SFRs */
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/* AUXR1 bits */
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#define DPS 0x01
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#define SRST 0x08
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#define LPEP 0x10
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#define BOI 0x20
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#define BOD 0x40
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#define KBF 0x80
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/* CMP1 bits */
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#define CMF1 0x01
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#define CO1 0x02
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#define OE1 0x04
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#define CN1 0x08
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#define CP1 0x10
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#define CE1 0x20
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/* CMP2 bits */
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#define CMF2 0x01
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#define CO2 0x02
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#define OE2 0x04
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#define CN2 0x08
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#define CP2 0x10
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#define CE2 0x20
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/* I2DAT bits */
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#define RDAT 0x80
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#define XDAT 0x80
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/* IP1H bits */
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#define PI2H 0x01
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#define PKBH 0x02
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#define PC2H 0x04
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#define PC1H 0x20
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#define PTIH 0x80
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/* PCON bits */
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#define IDL 0x01
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#define PD 0x02
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#define GF0 0x04
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#define GF1 0x08
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#define POF 0x10
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#define BOF 0x20
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#define SMOD0 0x40
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#define SMOD1 0x80
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/* P2M1 bits */
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#define ENT0 0x04
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#define ENT1 0x08
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#define ENTCLK 0x10
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#define P0S 0x20
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#define P1S 0x40
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#define P2S 0x80
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/* TMOD bits */
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#define M0_0 0x01
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#define M1_0 0x02
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#define C_T0 0x04
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#define GATE0 0x08
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#define M0_1 0x10
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#define M1_1 0x20
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#define C_T1 0x40
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#define GATE1 0x80
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/* WDCON bits */
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#define WDS0 0x01
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#define WDS1 0x02
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#define WDS2 0x04
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#define WDCLK 0x08
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#define WDRUN 0x10
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#define WDOVF 0x20
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/* Masks for I2CFG bits */
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#define BTIR 0x10 // Mask for TIRUN bit.
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#define BMRQ 0x40 // Mask for MASTRQ bit.
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#define BSLV 0x80 // Mask for SLAVEN bit.
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/* Masks for I2CON bits */
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#define BCXA 0x80 // Mask for CXA bit.
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#define BIDLE 0x40 // Mask for IDLE bit.
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#define BCDR 0x20 // Mask for CDR bit.
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#define BCARL 0x10 // Mask for CARL bit.
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#define BCSTR 0x08 // Mask for CSTR bit.
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#define BCSTP 0x04 // Mask for CSTP bit.
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#define BXSTR 0x02 // Mask for XSTR bit.
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#define BXSTP 0x01 // Mask for XSTP bit.
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#endif
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