159 lines
3.5 KiB
C
159 lines
3.5 KiB
C
/*-------------------------------------------------------------------------
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Register Declarations for 8051 Processor
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Written By - Sandeep Dutta . sandeep.dutta@usa.net (1998)
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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In other words, you are welcome to use, share and improve this program.
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You are forbidden to forbid anyone else to use, share and improve
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what you give them. Help stamp out software-hoarding!
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-------------------------------------------------------------------------*/
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#ifndef REG51_H
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#define REG51_H
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#warning This file (reg51.h) is obsolete, depending on your harware
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#warning use include <8051.h>, or include <8052.h>!
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/* BYTE Register */
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sfr at 0x80 P0 ;
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sfr at 0x90 P1 ;
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sfr at 0xA0 P2 ;
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sfr at 0xB0 P3 ;
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sfr at 0xD0 PSW ;
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sfr at 0xE0 ACC ;
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sfr at 0xF0 B ;
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sfr at 0x81 SP ;
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sfr at 0x82 DPL ;
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sfr at 0x83 DPH ;
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sfr at 0x87 PCON ;
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sfr at 0x88 TCON ;
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sfr at 0x89 TMOD ;
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sfr at 0x8A TL0 ;
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sfr at 0x8B TL1 ;
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sfr at 0x8C TH0 ;
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sfr at 0x8D TH1 ;
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sfr at 0x8E AUXR ;
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sfr at 0xA8 IE ;
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sfr at 0xB8 IP ;
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sfr at 0x98 SCON ;
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sfr at 0x99 SBUF ;
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/* BIT Register */
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/* PSW */
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sbit at 0xD7 CY ;
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sbit at 0xD6 AC ;
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sbit at 0xD5 F0 ;
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sbit at 0xD4 RS1 ;
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sbit at 0xD3 RS0 ;
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sbit at 0xD2 OV ;
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sbit at 0xD0 P ;
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/* TCON */
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sbit at 0x8F TF1 ;
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sbit at 0x8E TR1 ;
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sbit at 0x8D TF0 ;
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sbit at 0x8C TR0 ;
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sbit at 0x8B IE1 ;
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sbit at 0x8A IT1 ;
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sbit at 0x89 IE0 ;
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sbit at 0x88 IT0 ;
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/* IE */
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sbit at 0xAF EA ;
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sbit at 0xAC ES ;
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sbit at 0xAB ET1 ;
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sbit at 0xAA EX1 ;
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sbit at 0xA9 ET0 ;
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sbit at 0xA8 EX0 ;
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/* IP */
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sbit at 0xBC PS ;
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sbit at 0xBB PT1 ;
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sbit at 0xBA PX1 ;
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sbit at 0xB9 PT0 ;
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sbit at 0xB8 PX0 ;
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/* P3 */
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sbit at 0xB7 RD ;
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sbit at 0xB6 WR ;
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sbit at 0xB5 T1 ;
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sbit at 0xB4 T0 ;
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sbit at 0xB3 INT1 ;
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sbit at 0xB2 INT0 ;
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sbit at 0xB1 TXD ;
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sbit at 0xB0 RXD ;
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/* P1 */
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sbit at 0x90 P1_0 ;
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sbit at 0x91 P1_1 ;
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sbit at 0x92 P1_2 ;
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sbit at 0x93 P1_3 ;
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sbit at 0x94 P1_4 ;
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sbit at 0x95 P1_5 ;
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sbit at 0x96 P1_6 ;
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sbit at 0x97 P1_7 ;
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/* SCON */
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sbit at 0x9F SM0 ;
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sbit at 0x9E SM1 ;
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sbit at 0x9D SM2 ;
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sbit at 0x9C REN ;
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sbit at 0x9B TB8 ;
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sbit at 0x9A RB8 ;
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sbit at 0x99 TI ;
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sbit at 0x98 RI ;
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/* TMOD bits */
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#define GATE1 (1<<7)
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#define C_T1 (1<<6)
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#define M1_1 (1<<5)
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#define M0_1 (1<<4)
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#define GATE0 (1<<3)
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#define C_T0 (1<<2)
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#define M1_0 (1<<1)
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#define M0_0 (1<<0)
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/* T2CON */
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sfr at 0xC8 T2CON ;
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/* T2CON bits */
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sbit at 0xC8 T2CON_0 ;
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sbit at 0xC9 T2CON_1 ;
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sbit at 0xCA T2CON_2 ;
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sbit at 0xCB T2CON_3 ;
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sbit at 0xCC T2CON_4 ;
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sbit at 0xCD T2CON_5 ;
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sbit at 0xCE T2CON_6 ;
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sbit at 0xCF T2CON_7 ;
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/* RCAP2 L & H */
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sfr at 0xCB RCAP2H;
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sfr at 0xCA RCAP2L;
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#endif
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