342 lines
9.3 KiB
C
342 lines
9.3 KiB
C
/*-------------------------------------------------------------------------
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Register Declarations for ATMEL 89S8252 and 89LS8252 Processors
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Written By - Dipl.-Ing. (FH) Michael Schmitt
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mschmitt@mainz-online.de
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michael.schmitt@t-online.de
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Bug-Fix Jun 29 1999
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Additional definitions Nov 23 1999
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by Bernd Krueger-Knauber <bkk@infratec-plus.de>
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based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
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KEIL C compatible definitions are included
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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In other words, you are welcome to use, share and improve this program.
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You are forbidden to forbid anyone else to use, share and improve
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what you give them. Help stamp out software-hoarding!
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-------------------------------------------------------------------------*/
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#ifndef AT89S8252_H
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#define AT89S8252_H
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/* BYTE addressable registers */
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sfr at 0x80 P0 ;
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sfr at 0x81 SP ;
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sfr at 0x82 DPL ;
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sfr at 0x82 DP0L ; /* as called by Atmel */
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sfr at 0x83 DPH ;
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sfr at 0x83 DP0H ; /* as called by Atmel */
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sfr at 0x84 DP1L ; /* at89S8252 specific register */
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sfr at 0x85 DP1H ; /* at89S8252 specific register */
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sfr at 0x86 SPDR ; /* at89S8252 specific register */
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sfr at 0x87 PCON ;
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sfr at 0x88 TCON ;
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sfr at 0x89 TMOD ;
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sfr at 0x8A TL0 ;
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sfr at 0x8B TL1 ;
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sfr at 0x8C TH0 ;
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sfr at 0x8D TH1 ;
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sfr at 0x90 P1 ;
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sfr at 0x96 WMCON ; /* at89S8252 specific register */
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sfr at 0x98 SCON ;
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sfr at 0x99 SBUF ;
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sfr at 0xA0 P2 ;
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sfr at 0xA8 IE ;
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sfr at 0xAA SPSR ; /* at89S8252 specific register */
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sfr at 0xB0 P3 ;
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sfr at 0xB8 IP ;
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sfr at 0xC8 T2CON ;
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sfr at 0xC9 T2MOD ;
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sfr at 0xCA RCAP2L ;
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sfr at 0xCB RCAP2H ;
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sfr at 0xCC TL2 ;
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sfr at 0xCD TH2 ;
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sfr at 0xD0 PSW ;
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sfr at 0xD5 SPCR ; /* at89S8252 specific register */
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sfr at 0xE0 ACC ;
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sfr at 0xE0 A ;
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sfr at 0xF0 B ;
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/* BIT addressable registers */
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/* P0 */
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sbit at 0x80 P0_0 ;
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sbit at 0x81 P0_1 ;
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sbit at 0x82 P0_2 ;
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sbit at 0x83 P0_3 ;
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sbit at 0x84 P0_4 ;
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sbit at 0x85 P0_5 ;
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sbit at 0x86 P0_6 ;
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sbit at 0x87 P0_7 ;
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/* TCON */
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sbit at 0x88 IT0 ;
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sbit at 0x89 IE0 ;
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sbit at 0x8A IT1 ;
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sbit at 0x8B IE1 ;
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sbit at 0x8C TR0 ;
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sbit at 0x8D TF0 ;
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sbit at 0x8E TR1 ;
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sbit at 0x8F TF1 ;
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/* P1 */
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sbit at 0x90 P1_0 ;
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sbit at 0x91 P1_1 ;
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sbit at 0x92 P1_2 ;
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sbit at 0x93 P1_3 ;
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sbit at 0x94 P1_4 ;
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sbit at 0x95 P1_5 ;
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sbit at 0x96 P1_6 ;
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sbit at 0x97 P1_7 ;
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sbit at 0x90 T2 ;
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sbit at 0x91 T2EX ;
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/* P1 SPI portpins */
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sbit at 0x94 SS; /* SPI: SS - Slave port select input */
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sbit at 0x95 MOSI; /* SPI: MOSI - Master data output, slave data input */
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sbit at 0x96 MISO; /* SPI: MISO - Master data input, slave data output */
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sbit at 0x97 SCK; /* SPI: SCK - Master clock output, slave clock input */
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/* SCON */
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sbit at 0x98 RI ;
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sbit at 0x99 TI ;
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sbit at 0x9A RB8 ;
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sbit at 0x9B TB8 ;
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sbit at 0x9C REN ;
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sbit at 0x9D SM2 ;
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sbit at 0x9E SM1 ;
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sbit at 0x9F SM0 ;
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/* P2 */
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sbit at 0xA0 P2_0 ;
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sbit at 0xA1 P2_1 ;
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sbit at 0xA2 P2_2 ;
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sbit at 0xA3 P2_3 ;
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sbit at 0xA4 P2_4 ;
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sbit at 0xA5 P2_5 ;
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sbit at 0xA6 P2_6 ;
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sbit at 0xA7 P2_7 ;
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/* IE */
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sbit at 0xA8 EX0 ;
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sbit at 0xA9 ET0 ;
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sbit at 0xAA EX1 ;
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sbit at 0xAB ET1 ;
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sbit at 0xAC ES ;
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sbit at 0xAD ET2 ;
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sbit at 0xAF EA ;
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/* P3 */
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sbit at 0xB0 P3_0 ;
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sbit at 0xB1 P3_1 ;
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sbit at 0xB2 P3_2 ;
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sbit at 0xB3 P3_3 ;
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sbit at 0xB4 P3_4 ;
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sbit at 0xB5 P3_5 ;
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sbit at 0xB6 P3_6 ;
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sbit at 0xB7 P3_7 ;
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sbit at 0xB0 RXD ;
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sbit at 0xB1 TXD ;
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sbit at 0xB2 INT0 ;
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sbit at 0xB3 INT1 ;
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sbit at 0xB4 T0 ;
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sbit at 0xB5 T1 ;
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sbit at 0xB6 WR ;
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sbit at 0xB7 RD ;
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/* IP */
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sbit at 0xB8 PX0 ;
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sbit at 0xB9 PT0 ;
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sbit at 0xBA PX1 ;
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sbit at 0xBB PT1 ;
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sbit at 0xBC PS ;
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sbit at 0xBD PT2 ;
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/* T2CON */
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sbit at 0xC8 T2CON_0 ;
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sbit at 0xC9 T2CON_1 ;
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sbit at 0xCA T2CON_2 ;
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sbit at 0xCB T2CON_3 ;
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sbit at 0xCC T2CON_4 ;
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sbit at 0xCD T2CON_5 ;
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sbit at 0xCE T2CON_6 ;
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sbit at 0xCF T2CON_7 ;
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sbit at 0xC8 CP_RL2 ;
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sbit at 0xC9 C_T2 ;
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sbit at 0xCA TR2 ;
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sbit at 0xCB EXEN2 ;
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sbit at 0xCC TCLK ;
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sbit at 0xCD RCLK ;
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sbit at 0xCE EXF2 ;
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sbit at 0xCF TF2 ;
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/* PSW */
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sbit at 0xD0 P ;
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sbit at 0xD1 FL ;
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sbit at 0xD2 OV ;
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sbit at 0xD3 RS0 ;
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sbit at 0xD4 RS1 ;
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sbit at 0xD5 F0 ;
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sbit at 0xD6 AC ;
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sbit at 0xD7 CY ;
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/* B */
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sbit at 0xF0 BREG_F0 ;
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sbit at 0xF1 BREG_F1 ;
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sbit at 0xF2 BREG_F2 ;
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sbit at 0xF3 BREG_F3 ;
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sbit at 0xF4 BREG_F4 ;
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sbit at 0xF5 BREG_F5 ;
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sbit at 0xF6 BREG_F6 ;
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sbit at 0xF7 BREG_F7 ;
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/* BIT definitions for bits that are not directly accessible */
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/* PCON bits */
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#define IDL 0x01
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#define PD 0x02
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#define GF0 0x04
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#define GF1 0x08
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#define SMOD 0x80
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#define IDL_ 0x01
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#define PD_ 0x02
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#define GF0_ 0x04
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#define GF1_ 0x08
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#define SMOD_ 0x80
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/* TMOD bits */
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#define M0_0 0x01
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#define M1_0 0x02
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#define C_T0 0x04
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#define GATE0 0x08
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#define M0_1 0x10
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#define M1_1 0x20
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#define C_T1 0x40
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#define GATE1 0x80
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#define M0_0_ 0x01
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#define M1_0_ 0x02
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#define C_T0_ 0x04
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#define GATE0_ 0x08
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#define M0_1_ 0x10
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#define M1_1_ 0x20
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#define C_T1_ 0x40
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#define GATE1_ 0x80
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#define T0_M0 0x01
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#define T0_M1 0x02
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#define T0_CT 0x04
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#define T0_GATE 0x08
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#define T1_M0 0x10
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#define T1_M1 0x20
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#define T1_CT 0x40
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#define T1_GATE 0x80
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#define T0_M0_ 0x01
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#define T0_M1_ 0x02
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#define T0_CT_ 0x04
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#define T0_GATE_ 0x08
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#define T1_M0_ 0x10
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#define T1_M1_ 0x20
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#define T1_CT_ 0x40
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#define T1_GATE_ 0x80
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#define T0_MASK 0x0F
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#define T1_MASK 0xF0
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#define T0_MASK_ 0x0F
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#define T1_MASK_ 0xF0
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/* T2MOD bits */
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#define DCEN 0x01
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#define T2OE 0x02
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#define DCEN_ 0x01
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#define T2OE_ 0x02
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/* WMCON bits */
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#define WMCON_WDTEN 0x01
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#define WMCON_WDTRST 0x02
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#define WMCON_DPS 0x04
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#define WMCON_EEMEN 0x08
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#define WMCON_EEMWE 0x10
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#define WMCON_PS0 0x20
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#define WMCON_PS1 0x40
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#define WMCON_PS2 0x80
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/* SPCR-SPI bits */
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#define SPCR_SPR0 0x01
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#define SPCR_SPR1 0x02
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#define SPCR_CPHA 0x04
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#define SPCR_CPOL 0x08
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#define SPCR_MSTR 0x10
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#define SPCR_DORD 0x20
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#define SPCR_SPE 0x40
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#define SPCR_SPIE 0x80
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/* SPSR-SPI bits */
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#define SPSR_WCOL 0x40
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#define SPSR_SPIF 0x80
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/* SPDR-SPI bits */
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#define SPDR_SPD0 0x10
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#define SPDR_SPD1 0x20
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#define SPDR_SPD2 0x40
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#define SPDR_SPD3 0x80
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#define SPDR_SPD4 0x10
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#define SPDR_SPD5 0x20
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#define SPDR_SPD6 0x40
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#define SPDR_SPD7 0x80
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/* Interrupt numbers: address = (number * 8) + 3 */
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#define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
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#define EX0_VECTOR 0 /* 0x03 external interrupt 0 */
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#define TF0_VECTOR 1 /* 0x0b timer 0 */
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#define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
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#define EX1_VECTOR 2 /* 0x13 external interrupt 1 */
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#define TF1_VECTOR 3 /* 0x1b timer 1 */
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#define SI0_VECTOR 4 /* 0x23 serial port 0 */
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#define TF2_VECTOR 5 /* 0x2B timer 2 */
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#define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
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/* This is one of the addons comming from Bernd Krueger-Knauber */
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/* ALE (0x8E) Bit Values */
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sfr at 0x8E ALE; /* at89S8252 specific register */
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/* Macro to enable and disable the toggling of the ALE-pin (EMV) */
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/* Explanation : Orignal Intel 8051 Cores (Atmel has to use the */
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/* Intel Core) have a festure that ALE is only active during */
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/* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly */
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/* pulled high. This can be used to force some external devices */
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/* into stanby mode and reduced EMI noise */
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#define ALE_OFF ALE = ALE | 0x01
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#define ALE_ON ALE = ALE & 0xFE
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#endif
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