# Learning FPGAs #1

I normally work at the system or electronic level, and one thing I’ve always wanted to learn is FPGAs and the corresponding HDLs.

To pull this together, I plan to implement the 6502 using Verilog on an OrangeCrab board. The board uses a ECP5-25F and is supported by Yosys.

## 6502

I chose the 6502 as it reminds me of the VIC-20 and C128 I used to own, and it has a small, straight forward instruction set.

According to
https://llx.com/Neil/a2/opcodes.html, most instructions have a `aaabbbcc`

format, where `aaa`

and `cc`

determine the opcode and `bbb`

is the addressing mode.
https://www.pagetable.com/c64ref/6502/ has a nice 3-3-2 view of this.

The instructions are divided into groups based on `cc`

:

- 00 is group 3
- 01 is group 1
- 10 is group 2
- 11 is reserved

## Group 1 (c = 01)

Covers 1/4th of the decode space, where `aaa`

is:

- 000 ORA
- 001 AND
- 010 EOR
- 011 ADC
- 100 STA
- 101 LDA
- 110 CMP
- 111 SBC

and `bbb`

is:

- 000 (zero page,X)
- 001 zero page
- 010 #immediate
- 011 absolute
- 100 (zero page),Y
- 101 zero page,X
- 110 absolute,Y
- 111 absolute,X

## Group 2 (c = 10)

- 000 ASL
- 001 ROL
- 010 LSR
- 011 ROR
- 100 STX
- 101 LDX
- 110 DEC
- 111 INC

where `bbb`

is:

- 000 #immediate
- 001 zero page
- 010 accumulator
- 011 absolute
- 101 zero page,X
- 111 absolute,X

So zero page, absolute, zero page, X, and absolute, X are the same.

## Group 3 (c = 00)

- 001 BIT
- 010 JMP
- 011 JMP (abs)
- 100 STY
- 101 LDY
- 110 CPY
- 111 CPX

where `bbb`

is:

- 000 #immediate
- 001 zero page
- 011 absolute
- 101 zero page,X
- 111 absolute,X

which is the same as group 2 except `accumulator`

.

The conditional branches have the form `xxy 100 00`

, i.e. b is 100 and c is 00, and x is:

- 00 negative
- 01 overflow
- 10 carry
- 11 zero

which is compared with `y`

.

Next is to implement the ALU.